target.ref

vxworks pb926开发板的bsp包

HARDWARE DETAILS

\sh Devices
The device drivers included are:

    primeCellSio.c - PrimeCell UART driver.

If Flash support is configured then the following drivers are included:

   nvRamToFlash.c - NVRAM-to-Flash memory library

\sh Shared memory
This BSP has not been tested with shared memory, and there is no
BSP-specific support for test-and-set primitives.  The vxTas()
primitive is provided in the architecture-specific code to allow access
to the ARM SWPB instruction.  For further information, see the vxTas()
reference entry.

\sh Interrupts

22 interrupt levels are provided:
    0 Soft interrupt
    1 UART 0
    2 UART 1
    3 Keyboard
    4 Mouse
    5 Timer 0
    6 Timer 1
    7 Timer 2
    8 Real time clock
    9 Logic module 0
   10 Logic module 1
   11 Logic module 2
   12 Logic module 3
   13 PCI bus (INTA#)
   14 PCI bus (INTB#)
   15 PCI bus (INTC#)
   16 PCI bus (INTD#)
   17 V3 PCI bridge
   18 CompactPCI auxiliary interrupt (DEG#)
   19 CompactPCI auxiliary interrupt (ENUM#)
   20 PCI local bus fault
   21 External AutoPC

Only interrupt levels 1, 2, 5, 6, 13, 14, 15 and 16 are used by default
in this BSP.  Interrupt connection, enabling and disabling are
performed using the standard intArchLib routines.  The interrupt
controller driver is provided in ambaIntrCtl.c.

\sh Serial Configuration

There are two serial ports on the board, provided by two PrimeCell UARTs.
The default configuration is 9600 baud, 8 data bits, no parity, 1 stop
bit.

The driver code in primecellSio.c/.h is a modified version of the
standard VxWorks ambaSio driver.  Documentation for the PrimeCell UART
is on the ARM web site.

The two main differences are as follows:

The PrimeCell SIO has five separate interrupt signal lines.  Four of
these correspond to different types of interrupt; the fifth is a
combined signal, which is used on the Integrator to provide a single
interrupt source for each UART.

There are two separate interrupt signals for received data: one is
generated when the received buffer is more than half full; the other
when no data is received for 32 UART clocks.

\sh SCSI Configuration
This BSP does not support SCSI.

\sh Network Configuration
This BSP provides network support for PCI Dec 21x4x and Intel 8255x
network cards.

\sh VME Access
The board is a standalone board: VME is not supported.

\sh PCI Access
This BSP supports the PCI bus and has been tested with network
expansion cards.  PCI to PCI bridge functionality is not implemented.

\sh Boot Devices
By default, VxWorks is booted on this board by running the boot ROM
image from flash memory and loading the VxWorks kernel via the network
driver.

\sh Power Managment
Support is provided for power management.  This allows the core to sleep 
for periods of up to 700 ms.  The maximum sleep period is limited by 
the timer hardware.  If enabled, power managmenet uses Timer-2.  Power
management turns the processor clock off when the system is otherwise idle,
but keeps the system timer interrupt clock running.  The system goes into
a low power "sleep" mode until an interrupt wakes the system up.  Power 
management reschedules the system timer based on the time to the next 
scheduled system event.  When the system wakes up, it recomputes system 
time and adjusts the tick count.
  
Power managment is enabled in config.h by defining INCLUDE_POWER_MGMT_CPU_BSP_SUPPORT.

SPECIAL CONSIDERATIONS
\sh CPU Speed/Timers

Both the system timer and sleep timer are derived from the onboard 24 mhz 
reference clock.  For the system timer, this clock rate is divided by 16.  
During extened sleep periods, the timer prescaller is set to 256.  As 
noted in the BSP developer's guide, selecting a tick rate that is not a 
multiple of the timer clock reference will result in tick period inaccuracy.  
If power managmenet is enabled, it is important to divide the system clock
by 256 before selecting a tick rate.  Otherwise, an accurate tick rate can 
be obtained by dividing the 24 mhz reference by 16. 

All clocks are derived from various VCOs and dividers, which can be
modified under software control.  Clock values are read throuh the 
coprocessor are set according to the header fitted (cf. romInit.s).

\sh Special routines
The routine sysLedsReadWrite() is used to control the LEDs on the
board.  Use of the LEDs is mutually exclusive with use of the parallel
port due to a restriction in the hardware.  For further information,
see the reference entry for this routine.

\sh Divide by Zero Exception
The ARM architecture does not provide for an integer divide by zero
exception.  Consequently, no exception is generated when an integer
divide by zero operation is performed programmatically.

\sh Multiple core module support
Support is provided for only one core module.

BOARD LAYOUT
The diagrams below show the relevant jumpers for VxWorks
configuration.
\bs

______________________________________________________________________________
|               +---+ +---+ +---+ +---+    J15                               |
|         LOGIC | U | | U | | U | | U |    +-+                             +-+
|          +-+  |11 | |12 | |13 | |14 |    | |                          J21| |
|+-------+ | |  +---+ +---+ +---+ +---+    | |                             | |
|| J12   + | |  +---+ +---+ +---+ +---+    | |                             +-+
|+-------+ | |  | U | | U | | U | | U |    | |                       S3   S2 |
|          +-+  |15 | |16 | |17 | |18 |    | |                               |
|               +---+ +---+ +---+ +---+    | |                               |
|               +-----+                    | |                               |
|           U34 |SRAM |   ----EXPM----     +-+                               |
|               +-----+             +---+                                    |
|--+            +-----+             |U19|                                    |
|  |ALPHA   U35 |SRAM |             +---+                                    |
|  |DISPLAY     +-----+           +-----+                                    |
|--+                              | V3  |                                    |
|                                 +-----+                                    |
|    +----------------------------+       +-+ +-+ +-+                        |
|    |                            |       | | | | | |                       +--+
|    |                            |       |P| |P| |P|                       |C |
|    |               +-------+    |       |C| |C| |C|                       |O |
|    |               |  FPGA |    |       |I| |I| |I|                       |M |
+-+  | +------+      |       |    |       | | | | | |                       |P |
|A|  | |  CPU |      +-------+    |       |S| |S| |S|                       |A |
|T|  | |      |                   |       |L| |L| |L|                       |C |
|X|  | +----- +                   |       |O| |O| |O|                       |T |
+-+  |                            |       |T| |T| |T|            +--------+ |  |
|    +----------------------------+       | | | | | |            | PCI/PCI| |P |
|KBD                                      +-+ +-+ +-+            | Bridge | |C |
+--+      SERIAL SERIAL                   J9  J10 J11            +--------+ |I |
|  |  S1  +----+ +----+                                                     +--+
|__|______|    |_|    |_____________________    ______________________________|
\be
    Key:
    S1    4 pole DIL switch
    S2    Reset button
    S3    Standby button

    U11.. Flash memory
    U19   Boot ROM
    J15   Logic module connector (EXPA) 
    EXPM  External bus interface connector
    V3    System bus - PCI bridge

SEE ALSO
\tb Tornado User's Guide: Getting Started, 
\tb VxWorks Programmer's Guide: Configuration. 

BIBLIOGRAPHY
\tb ARM Integrator/AP User Guide ,
\tb ARM Integrator/CM926EJ-S User Guide ,
\tb ARM Architecture Reference Manual ,
\tb ARM 926EJ-S Technical Reference Manual ,
\tb ARM Reference Peripherals Specification .