reg4052.h

基本STC4052写的一个小的OS, 完成了任务调度功能,及堆栈空间切换, 及中断处理

//---------------------------------------------------------------
//      
//       Copyright (c) 2006-2007 E-compass electronic Co.,Ltd.               
//       All Right Reserved.                                     
//                                                               
//       $Author    walnutcy
//       $Email     [e-mail]              
//       $Version   v1.0  
//       $FileName                                       
//       $Since                                            
//       $Log                                                    
//                                                               
//       DESCRIPTION   
//
//		 History:         
//		 <author>          <time>     <version >    <desc> 
//---------------------------------------------------------------
#ifndef _REG_STC12_H
#define _REG_STC12_H

sfr P0   = 0x80;
sfr P1   = 0x90;
sfr P2   = 0xA0;
sfr P3   = 0xB0;

sfr PSW  = 0xD0;
sfr ACC  = 0xE0;
sfr B    = 0xF0;
sfr SP   = 0x81;
sfr DPL  = 0x82;
sfr DPH  = 0x83;

// Timer SFRs
//-------------------------
sfr TMOD = 0x89;
sfr TL0  = 0x8A;
sfr TL1  = 0x8B;
sfr TH0  = 0x8C;
sfr TH1  = 0x8D;

// interrupt SFRs
//-------------------------
sfr IE   = 0xA8;
sfr IP   = 0xB8;
sfr IPH	 = 0xB7;
sfr SBUF = 0x99;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr SCON = 0x98;
sfr AUXR = 0x8E;
sfr CCON = 0xD8;
sfr CMOD = 0xD9;
sfr CCAPM0    = 0xDA;
sfr CCAPM1    = 0xDB;
sfr SPSTAT	  = 0x84;

//---ADC
//--------------------
sfr ADC_DATA	= 0xC6;
sfr ADC_CONTR = 0xC5;

///////////////////////////////////////////

//----Byte Register
//-----------------------------
sfr SPCTL	= 0x85;
sfr SPDAT	= 0x86;
sfr P1M0		= 0x91;
sfr P1M1		= 0x92;
sfr P3M0		= 0xB1;
sfr P3M1		= 0xB2;
sfr IDLE_CLK	= 0xC7;

// Watch Dog SFRs
//-----------------------------
sfr WDT_CONTR   = 0xE1;

// ISP SFRs
//----------------------------
sfr ISP_DATA		= 0xE2;
sfr ISP_ADDRH   	= 0xE3;
sfr ISP_ADDRL   	= 0xE4;
sfr ISP_CMD     	= 0xE5;
sfr ISP_TRIG    	= 0xE6;
sfr ISP_CONTR   	= 0xE7;

// PCA/PWM SFRs
//---------------------------
sfr CL      	= 0xE9;
sfr CH      	= 0xF9;
sfr CCAP0L  	= 0xEA;
sfr CCAP0H  	= 0xFA;
sfr CCAP1L  	= 0xEB;
sfr CCAP1H  	= 0xFB;
sfr PCAPWM0 	= 0xF2;
sfr PCAPWM1 	= 0xF3;

// Bit Register
//---------------------------
// IE
sbit EPCA       = IE^6;
// CCON
sbit CF         = CCON^7;
sbit CR         = CCON^6;
sbit CCF1       = CCON^1;
sbit CCF0       = CCON^0;

/*  PSW   */
sbit CY   = 0xD7;
sbit AC   = 0xD6;
sbit F0   = 0xD5;
sbit RS1  = 0xD4;
sbit RS0  = 0xD3;
sbit OV   = 0xD2;
sbit P    = 0xD0;

/*  TCON  */
sbit TF1  = 0x8F;
sbit TR1  = 0x8E;
sbit TF0  = 0x8D;
sbit TR0  = 0x8C;
sbit IE1  = 0x8B;
sbit IT1  = 0x8A;
sbit IE0  = 0x89;
sbit IT0  = 0x88;

/*  IE   */
sbit EA   = 0xAF;
sbit ES   = 0xAC;
sbit ET1  = 0xAB;
sbit EX1  = 0xAA;
sbit ET0  = 0xA9;
sbit EX0  = 0xA8;

/*  IP   */ 
sbit PS   = 0xBC;
sbit PT1  = 0xBB;
sbit PX1  = 0xBA;
sbit PT0  = 0xB9;
sbit PX0  = 0xB8;

/*  P3  */
sbit RD   = 0xB7;
sbit WR   = 0xB6;
sbit T1   = 0xB5;
sbit T0   = 0xB4;
sbit INT1 = 0xB3;
sbit INT0 = 0xB2;
sbit TXD  = 0xB1;
sbit RXD  = 0xB0;

/*  SCON  */
sbit SM0  = 0x9F;
sbit SM1  = 0x9E;
sbit SM2  = 0x9D;
sbit REN  = 0x9C;
sbit TB8  = 0x9B;
sbit RB8  = 0x9A;
sbit TI   = 0x99;
sbit RI   = 0x98;


#endif