📄 hardware.lst
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00009321 09 23 40 00 r1 -= 0x40;
00009323 19 D3 17 70 [P_DAC1] = r1;
00009325 4A 4E jnz L_RD_Loop;
L_RD_End:
00009326 90 90 pop r1,r2 from [sp];
00009327 90 9A retf;
.ENDP
///////////////////////////////////////
_SP_RampUpDAC2: .PROC
F_SP_RampUpDAC2:
00009328 90 D4 push r1,r2 to [sp];
00009329 11 93 16 70 r1=[P_DAC2];
0000932B 09 B3 C0 FF r1 &= ~0x003f;
0000932D 09 43 00 80 cmp r1,0x8000
0000932F 0E 0E jb L_RU_NormalUp_;
00009330 5D 5E je L_RU_End;
L_RU_DownLoop_:
00009331 40 F0 5E 93 call F_Delay;
00009333 41 94 r2 = 0x0001;
00009334 1A D5 12 70 [P_Watchdog_Clear] = r2;
00009336 09 23 40 00 r1 -= 0x40;
00009338 19 D3 16 70 [P_DAC2] = r1;
0000933A 09 43 00 80 cmp r1,0x8000;
0000933C 4C 4E jne L_RU_DownLoop_;
L_RD_DownEnd_:
0000933D 0C EE jmp L_RU_End_;
L_RU_NormalUp_:
L_RU_Loop_:
0000933E 40 F0 5E 93 call F_Delay;
00009340 41 94 r2 = 0x0001;
00009341 1A D5 12 70 [P_Watchdog_Clear] = r2;
00009343 09 03 40 00 r1 += 0x40;
00009345 19 D3 16 70 [P_DAC2] = r1;
00009347 09 43 00 80 cmp r1, 0x8000;
00009349 4C 4E jne L_RU_Loop_;
L_RU_End_:
0000934A 90 90 pop r1,r2 from [sp];
0000934B 90 9A retf;
.ENDP
///////////////////////////////////////
_SP_RampDnDAC2: .PROC
F_SP_RampDnDAC2:
//int off;
0000934C 90 D4 push r1,r2 to [sp];
0000934D 11 93 16 70 r1 = [P_DAC2];
0000934F 09 B3 C0 FF r1 &= ~0x003F;
00009351 0A 5E jz L_RD_End_;
L_RD_Loop_:
00009352 40 F0 5E 93 call F_Delay;
00009354 41 94 r2 = 0x0001;
00009355 1A D5 12 70 [P_Watchdog_Clear] = r2;
00009357 09 23 40 00 r1 -= 0x40;
00009359 19 D3 16 70 [P_DAC2] = r1;
0000935B 4A 4E jnz L_RD_Loop_;
L_RD_End_:
0000935C 90 90 pop r1,r2 from [sp];
0000935D 90 9A retf;
.ENDP
////////////////////////////////////////
F_Delay:
0000935E 88 D2 push r1 to [sp];
0000935F 48 92 r1 = 8;
L_D_Loop:
00009360 41 22 r1 -= 1;
00009361 42 4E jnz L_D_Loop;
00009362 88 90 pop r1 from [sp];
00009363 90 9A retf;
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,R2
///////////////////////////////////////////
F_SP_InitQueue:
00009364 09 93 20 03 R1 = R_Queue;
00009366 40 94 R2 = 0;
L_ClearQueueLoop:
00009367 D1 D4 [R1++] = R2;
00009368 09 43 52 03 cmp R1, R_Queue+C_QueueSize;
0000936A 44 4E jne L_ClearQueueLoop;
0000936B 40 92 R1 = 0;
0000936C 19 D3 52 03 [R_ReadIndex] = R1;
0000936E 19 D3 53 03 [R_WriteIndex] = R1;
00009370 90 9A retf;
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue:
00009371 12 95 52 03 R2 = [R_ReadIndex];
00009373 12 45 53 03 cmp R2,[R_WriteIndex];
00009375 0C 5E je L_RQ_QueueEmpty;
00009376 0A 05 20 03 R2 += R_Queue; // get queue data address
00009378 C2 92 R1 = [R2];
00009379 12 95 52 03 R2 = [R_ReadIndex];
0000937B 41 04 R2 += 1;
0000937C 72 44 cmp R2, C_QueueSize;
0000937D 01 4E jne L_RQ_NotQueueBottom;
0000937E 40 94 R2 = 0;
L_RQ_NotQueueBottom:
0000937F 1A D5 52 03 [R_ReadIndex] = R2;
//r2 = 0x0000; // get queue data
00009381 90 9A retf;
L_RQ_QueueEmpty:
//r2 = 0x8000; // queue empty
00009382 90 9A retf;
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2,R3
///////////////////////////////////////////
F_SP_WriteQueue:
00009383 12 95 53 03 R2 = [R_WriteIndex]; // put data to queue
00009385 0A 05 20 03 R2 += R_Queue;
00009387 C2 D2 [R2] = R1;
00009388 12 95 53 03 R2 = [R_WriteIndex];
0000938A 41 04 R2 += 1;
0000938B 72 44 cmp R2, C_QueueSize;
0000938C 01 4E jne L_WQ_NotQueueBottom;
0000938D 40 94 R2 = 0;
L_WQ_NotQueueBottom:
0000938E 1A D5 53 03 [R_WriteIndex] = R2;
00009390 90 9A retf;
//..........................................
F_SP_TestQueue:
//... Test Queue Empty ...
00009391 11 93 52 03 R1 = [R_ReadIndex];
00009393 11 43 53 03 cmp R1,[R_WriteIndex];
00009395 11 5E je L_TQ_QueueEmpty;
//... Test Queue Full ...
00009396 11 93 52 03 R1 = [R_ReadIndex]; // For N Queue Full: 1. W=R-1 2.R=0/W=N-1
00009398 04 4E jnz L_TQ_JudgeCond2;
00009399 11 93 53 03 R1 = [R_WriteIndex];
0000939B 71 42 cmp R1, C_QueueSize-1; // Cond1
0000939C 08 5E je L_TQ_QueueFull;
L_TQ_JudgeCond2:
0000939D 11 93 52 03 R1 = [R_ReadIndex];
0000939F 41 22 R1 -=1;
000093A0 11 43 53 03 cmp R1,[R_WriteIndex];
000093A2 02 5E je L_TQ_QueueFull;
000093A3 40 92 r1 = 0; // not Full, not empty
000093A4 90 9A retf;
L_TQ_QueueFull:
000093A5 41 92 r1 = 1; // full
000093A6 90 9A retf;
L_TQ_QueueEmpty:
000093A7 42 92 r1 = 2; // empty
000093A8 90 9A retf;
//.........................................
//////////////////////////////////////////////////////
// SACM_GetResource(Address,Page,offset);
//////////////////////////////////////////////////////
_SP_GetResource: .PROC
000093A9 88 DA push bp to [sp];
000093AA 08 0B 01 00 bp = sp + 1;
//push r2 to [sp];
000093AC 03 92 r1 = [bp+3]; // address
000093AD 04 94 r2 = [bp+4]; // bank
000093AE 5A 95 r2 = r2 lsl 4;
000093AF 5A 95 r2 = r2 lsl 4;
000093B0 4A 95 r2 = r2 lsl 2;
000093B1 7F BC sr &= 0x03f;
000093B2 06 A5 r2 |=sr;
000093B3 02 9D sr = r2;
000093B4 E1 92 r1 = D:[r1];
//pop r2 from [sp];
000093B5 88 98 pop bp from [sp];
000093B6 90 9A retf;
.ENDP
_SP_Delay: .PROC
F_SP_Delay:
000093B7 90 9A retf;
.ENDP
//========================================================================================
// End of hardware.asm
//========================================================================================
0 error(s), 0 warning(s).
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