📄 dma4.c
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/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) DSP/BIOS 4.90.150 04-08-03 (barracuda-m02)" */
/******************************************************************************\
* Copyright (C) 2000 Texas Instruments Incorporated.
* All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... dma4.c
* DATE CREATED.. 01/11/2000
* LAST MODIFIED. 12/29/2000
\******************************************************************************/
#include <stdio.h>
#include <math.h>
#include <csl.h>
#include <csl_dma.h>
#include <csl_mcbsp.h>
#include <csl_irq.h>
#include "tms320.h"
#include "dsplib.h"
volatile unsigned int *SWWSR=(unsigned int*)0x28;
volatile unsigned int *CMDCLK=(unsigned int*)0x58;
/*----------------------------------------------------------------------------*/
/* In this example, DATA is buffered in DMA channel 3 to be written */
/* via DXR to be recieved via DRR into a buffer in DMA channel 2 */
/* These are the settings for the DMA mode control register to */
/* enable DMA channel 3 to be configured as a transmit buffer for */
/* MCBSP 0 */
/* DMMCR3 = 0x5341u */
/* #0101001101000001b */
/* ;0~~~~~~~~~~~~~~~ (AUTOINIT) Autoinit disabled */
/* ;~1~~~~~~~~~~~~~~ (DINM) Interrupts enabled */
/* ;~~0~~~~~~~~~~~~~ (IMOD) N/A */
/* ;~~~1~~~~~~~~~~~~ (CTMOD) DMA is in ABU mode */
/* ;~~~~0~~~~~~~~~~~ N/A */
/* ;~~~~~011~~~~~~~~ (SIND) Src post-increment with IDX0 */
/* ;~~~~~~~~01~~~~~~ (DMS) Src in data space */
/* ;~~~~~~~~~~0~~~~~ N/A */
/* ;~~~~~~~~~~~000~~ (DIND) Dst No address mod (MCBSP DXR) */
/* ;~~~~~~~~~~~~~~01 (DMD) Dst in data space */
/* These are the settings required for the DMA sync and frame count */
/* register, DMSFC, to sync DMA channel 3 with MCBSP0 transmit */
/* DMSFC3 = 0x2800u */
/* #0000000000000000b */
/* ;0010~~~~~~~~~~~~ (DSYN) Sync with MCBSP XEVT0 */
/* ;~~~~1~~~~~~~~~~~ (DBLW) Double-word mode */
/* ;~~~~~000~~~~~~~~ N/A */
/* ;~~~~~~~~00000000 (Frame Count) Frame Count = 0h (one frame) */
/* These are thesettingrequired for DMA channel 2 to be configured */
/* as a receive buffer for MCBSP 0 */
/* DMMCR2 = 0x504Du */
/* #0101000001001101b */
/* ;0~~~~~~~~~~~~~~~ (AUTOINIT) Autoinit disabled */
/* ;~1~~~~~~~~~~~~~~ (DINM) Interrupts enabled */
/* ;~~0~~~~~~~~~~~~~ (IMOD) N/A */
/* ;~~~1~~~~~~~~~~~~ (CTMOD) DMA is in ABU mode */
/* ;~~~~0~~~~~~~~~~~ N/A */
/* ;~~~~~000~~~~~~~~ (SIND) No src modification (MCBSP DRR) */
/* ;~~~~~~~~01~~~~~~ (DMS) Src in data space */
/* ;~~~~~~~~~~0~~~~~ N/A */
/* ;~~~~~~~~~~~011~~ (DIND) DST post increment with DMIDX0 */
/* ;~~~~~~~~~~~~~~01 (DMD) Dst in data space */
/* These are the settings forthe DMA ync and frame count register */
/* to sync DMA channel 2 with MCBSP0 receive */
/* DMSFC3 = 0x1800u */
/* #0001000000000000b */
/* ;0001~~~~~~~~~~~~ (DSYN) Sync with MCBSP REVT0 */
/* ;~~~~1~~~~~~~~~~~ (DBLW) Double-word mode */
/* ;~~~~~000~~~~~~~~ Reserved */
/* ;~~~~~~~~00000000 (Frame Count) Frame Count = 0h (one frame) */
/* These are the settings for the MCBSP control registers to place */
/* the MCBSP in digital loopback mode, using the sample rate */
/* generator to drive the frame sync. */
/* SPCR10 = 0x8000 */
/* #1000000000000000B */
/* ;1~~~~~~~~~~~~~~~ DLB Loopback mode */
/* ;~00~~~~~~~~~~~~~ RJUST Right-justify/zer-fill DRR's */
/* ;~~~00~~~~~~~~~~~ CLKSTP Continuous clock mode */
/* ;~~~~~000~~~~~~~~ N/A */
/* ;~~~~~~~~0~~~~~~~ DXENA DX delay off */
/* ;~~~~~~~~~0~~~~~~ ABIS A-bis mode disabled */
/* ;~~~~~~~~~~00~~~~ RINTM Interrupt generated on RRDY */
/* ;~~~~~~~~~~~~0~~~ RSYNCERR Clear sync error */
/* ;~~~~~~~~~~~~~0~~ RFULL */
/* ;~~~~~~~~~~~~~~0~ RRDY */
/* ;~~~~~~~~~~~~~~~0 RRST- Serial port in Reset */
/* */
/* SPCR20 = 0x0000 */
/* #0000000000000000b */
/* ;000000~~~~~~~~~~ Reserved */
/* ;~~~~~~0~~~~~~~~~ Free Free run disabled */
/* ;~~~~~~~0~~~~~~~~ Soft Disabled */
/* ;~~~~~~~~0~~~~~~~ FRST- Frame sync generator in reset */
/* ;~~~~~~~~~0~~~~~~ GRST- Clock generator in reset */
/* ;~~~~~~~~~~00~~~~ XINTM Transmit interrupt on XRDY */
/* ;~~~~~~~~~~~~0~~~ XSYNCERR Clear sync error */
/* ;~~~~~~~~~~~~~0~~ XEMPTY- */
/* ;~~~~~~~~~~~~~~0~ XRDY */
/* ;~~~~~~~~~~~~~~~0 XRST- Transmitter in reset */
/* */
/* RCR1_0 = 0x0040 */
/* #0000000001000000b */
/* ;0~~~~~~~~~~~~~~~ Reserved */
/* ;~0000000~~~~~~~~ RFRLEN1 One frame (0h) */
/* ;~~~~~~~~010~~~~~ RWDLEN1 16-bit words */
/* ;~~~~~~~~~~~00000 Reserved */
/* */
/* RCR2_0 = 0x0001 */
/* #0000000000000001b */
/* ;0~~~~~~~~~~~~~~~ RPHASE Single phase frames */
/* ;~0000000~~~~~~~~ RFRLEN2 N/A */
/* ;~~~~~~~~000~~~~~ RWDLEN2 N/A */
/* ;~~~~~~~~~~~00~~~ RCOMPAND No companding */
/* ;~~~~~~~~~~~~~0~~ RFIG Receive frame ignore off */
/* ;~~~~~~~~~~~~~~01 RDATDLY 1-bit delay */
/* */
/* XCR1_0 = 0x0040 */
/* #0000000001000000b */
/* ;0~~~~~~~~~~~~~~~ Reserved */
/* ;~0000000~~~~~~~~ XFRLEN1 One word frames */
/* ;~~~~~~~~010~~~~~ XWDLEN1 16-bit words */
/* ;~~~~~~~~~~~00000 Reserved */
/* */
/* XCR2_0 = 0x0001 */
/* #0000000000000001b */
/* ;0~~~~~~~~~~~~~~~ XPHASE Single phase */
/* ;~0000000~~~~~~~~ XFRLEN2 N/A */
/* ;~~~~~~~~000~~~~~ XWDLEN2 N/A */
/* ;~~~~~~~~~~~00~~~ XCOMPAND No companding */
/* ;~~~~~~~~~~~~~0~~ XFIG Transmit frame ignore off */
/* ;~~~~~~~~~~~~~~01 XDATDLY 1-bit delay */
/* */
/* SRGR1_0 */
/* #0000000000000000b */
/* ;00000000~~~~~~~~ FWID Frame sync is one cycle wide */
/* ;~~~~~~~~00000000 CLKGDV Clock is divided by one */
/* */
/* SRGR2_0 = 0x4000 */
/* #0010000000000000b */
/* ;0~~~~~~~~~~~~~~~ GSYNC No re-sync */
/* ;~0~~~~~~~~~~~~~~ CLKSP Normal clock edge polarity */
/* ;~~1~~~~~~~~~~~~~ CLKSM Clock from CPU source (not CLKS)*/
/* ;~~~0~~~~~~~~~~~~ FSGM Transmit due to DXR-to-XSR copy */
/* ;~~~~000000000000 FPER N/A */
/* */
/* PCR0 = 0x0a00 */
/* #0000101000000000b */
/* ;00~~~~~~~~~~~~~~ N/A */
/* ;~~0~~~~~~~~~~~~~ XIOEN No general purpose I/O's */
/* ;~~~0~~~~~~~~~~~~ RIOEN No general purpose I/O's */
/* ;~~~~1~~~~~~~~~~~ FSXM FSX from internal source */
/* ;~~~~~0~~~~~~~~~~ FSRM FSR from external source */
/* ;~~~~~~1~~~~~~~~~ CLKXM BCLKX from internal source */
/* ;~~~~~~~1~~~~~~~~ CLKRM BCLKR from BCLKX in DLB mode */
/* ;~~~~~~~~0~~~~~~~ N/A */
/* ;~~~~~~~~~0~~~~~~ CLKS_STAT */
/* ;~~~~~~~~~~0~~~~~ DX_STAT */
/* ;~~~~~~~~~~~0~~~~ DR_STAT */
/* ;~~~~~~~~~~~~0~~~ FSXP FSX is active high */
/* ;~~~~~~~~~~~~~0~~ FSRP FSR is active high */
/* ;~~~~~~~~~~~~~~0~ CLKXP Normal BCLKX polarity */
/* ;~~~~~~~~~~~~~~~0 CLKRP Normal BCLKR polarity */
/* Create data buffers for DMA/MCBSP transfer */
#define Nm2 1024
#define N 512
#define Nd2 256
#define Nd4 128
#define Nd8 64
Uint32 Dis[Nd2];
Uint32 dsttemp;
Uint16 PingPong=1;
#pragma DATA_SECTION(src,"dmaSrc")
Uint32 src[N];
#pragma DATA_SECTION(dst, "dmaDst")
Uint32 dst[N];
#pragma DATA_SECTION(LchIn, "dmaLin")
DATA LchIn[Nd4];
#pragma DATA_SECTION(RchIn, "dmaRin")
DATA RchIn[Nd4];
#pragma DATA_SECTION(Ly, "Lyin")
Uint32 Ly[Nd8];
#pragma DATA_SECTION(Ry, "Ryin")
Uint32 Ry[Nd8];
Uint32 LySend[32];
/*
#pragma DATA_SECTION(SAA,".databuf")
DATA SAA[64];
*/
/* Get Reference to start of interrupt vector table */
/* This symbol is defined in file, vectors.s54 */
extern void VECSTART(void);
/* Create configuration structure for MCBSP 0, using predefined */
/* CSL macros and symbolic constants */
MCBSP_Config my_mcbspConfig = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF,
MCBSP_SPCR1_RJUST_DEFAULT,
MCBSP_SPCR1_CLKSTP_DISABLE,
MCBSP_SPCR1_DXENA_DEFAULT,
MCBSP_SPCR1_RINTM_RRDY,
MCBSP_SPCR1_RRST_DISABLE
), /* SPCR1 */
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO,
MCBSP_SPCR2_SOFT_NO,
MCBSP_SPCR2_FRST_FSG,
MCBSP_SPCR2_GRST_CLKG,
MCBSP_SPCR2_XINTM_XRDY,
MCBSP_SPCR2_XRST_DISABLE
), /* SPCR2 */
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(1),
MCBSP_RCR1_RWDLEN1_32BIT
), /* RCR1 */
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_DUAL,
MCBSP_RCR2_RFRLEN2_OF(1),
MCBSP_RCR2_RWDLEN2_32BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_YES,
MCBSP_RCR2_RDATDLY_0BIT
), /* RCR2 */
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(1),
MCBSP_XCR1_XWDLEN1_32BIT
), /* XCR1 */
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_DUAL,
MCBSP_XCR2_XFRLEN2_OF(1),
MCBSP_XCR2_XWDLEN2_32BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_YES,
MCBSP_XCR2_XDATDLY_0BIT
), /* XCR2 */
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(31),
MCBSP_SRGR1_CLKGDV_OF(39)
), /* SRGR1 */
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_FALLING,
MCBSP_SRGR2_CLKSM_INTERNAL,
MCBSP_SRGR2_FSGM_FSG,
MCBSP_SRGR2_FPER_OF(63)
), /* SRGR2 */
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_DEFAULT,
MCBSP_PCR_RIOEN_DEFAULT,
MCBSP_PCR_FSXM_INTERNAL,
MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
MCBSP_PCR_CLKXM_OUTPUT,
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_FSXP_ACTIVEHIGH,
MCBSP_PCR_FSRP_ACTIVEHIGH,
MCBSP_PCR_CLKXP_FALLING,
MCBSP_PCR_CLKRP_RISING
), /* PCR */
0x0000u, /* RCERA */
0x0000u, /* RCERB */
0x0000u, /* XCERA */
0x0000u, /* XCERB */
};
MCBSP_Config my_mcbspConfig1 = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF,
MCBSP_SPCR1_RJUST_DEFAULT,
MCBSP_SPCR1_CLKSTP_NODELAY,
MCBSP_SPCR1_DXENA_DEFAULT,
MCBSP_SPCR1_RINTM_RRDY,
MCBSP_SPCR1_RRST_DISABLE
), /* SPCR1 */
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO,
MCBSP_SPCR2_SOFT_NO,
MCBSP_SPCR2_FRST_FSG,
MCBSP_SPCR2_GRST_CLKG,
MCBSP_SPCR2_XINTM_XRDY,
MCBSP_SPCR2_XRST_DISABLE
), /* SPCR2 */
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_DEFAULT,
MCBSP_RCR1_RWDLEN1_16BIT
), /* RCR1 */
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE,
MCBSP_RCR2_RFRLEN2_DEFAULT,
MCBSP_RCR2_RWDLEN2_16BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_YES,
MCBSP_RCR2_RDATDLY_0BIT
), /* RCR2 */
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_DEFAULT,
MCBSP_XCR1_XWDLEN1_32BIT
), /* XCR1 */
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE,
MCBSP_XCR2_XFRLEN2_OF(0),
MCBSP_XCR2_XWDLEN2_32BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_YES,
MCBSP_XCR2_XDATDLY_0BIT
), /* XCR2 */
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0),
MCBSP_SRGR1_CLKGDV_OF(1)
), /* SRGR1 */
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_RISING,
MCBSP_SRGR2_CLKSM_INTERNAL,
MCBSP_SRGR2_FSGM_DEFAULT,
MCBSP_SRGR2_FPER_DEFAULT
), /* SRGR2 */
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_DEFAULT,
MCBSP_PCR_RIOEN_DEFAULT,
MCBSP_PCR_FSXM_EXTERNAL,
MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
MCBSP_PCR_CLKXM_INPUT,
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_FSXP_ACTIVELOW,
MCBSP_PCR_FSRP_ACTIVELOW,
MCBSP_PCR_CLKXP_RISING,
MCBSP_PCR_CLKRP_RISING
), /* PCR */
0x0000u, /* RCERA */
0x0000u, /* RCERB */
0x0000u, /* XCERA */
0x0000u, /* XCERB */
};
/* Create a configuration structure for DMa channel 5 using */
/* predefined CSL macros and symbolic constants */
DMA_Config my_dmaConfigCha5 = {
1, /* Priority */
DMA_DMMCR_RMK(
DMA_DMMCR_AUTOINIT_OFF,
DMA_DMMCR_DINM_ON,
DMA_DMMCR_IMOD_HALF_AND_FULL,
DMA_DMMCR_CTMOD_ABU,
// DMA_DMMCR_CTMOD_MULTIFRAME,
DMA_DMMCR_SLAXS_OFF,
DMA_DMMCR_SIND_DMIDX0,
DMA_DMMCR_DMS_DATA,
DMA_DMMCR_DLAXS_OFF,
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