test.v

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//`timescale 1ns/1ns
module main;

  wire cycle ;
  wire write ;
  wire ifetch ;
  wire iack ;
  wire ie ;
  wire [15:0] address ;
  wire [7:0] data_out ;
  wire scan_out ;
  reg clk ;
  wire clk_w ;
  reg rst_n ;
  wire rst_n_w ;
  reg nmi ;
  wire nmi_w ;
  reg  int ;
  wire int_w ;
  wire ready_w ;
  reg  [7:0] data_in ;
  wire [7:0] data_in_w ;
  reg scan_in ;
  wire scan_in_w ;
  reg scan_en ;
  wire scan_en_w ;
  reg scan_mode ;
  wire scan_mode_w ;

  reg [7:0] int_vector;
  reg [7:0] ready_cntrl;
  reg [15:0] address_d;
  reg [15:0] address_dd;
  reg [15:0] address_ddd;
  reg [15:0] address_dddd;

  reg [7:0]  mem [0:65535];

  assign data_in_w = (cycle & ~write & ~iack)? mem[address[15:0]] : 
                     int_vector;

  assign clk_w = clk ;
  assign rst_n_w = rst_n ;
  assign nmi_w = nmi ;
  assign int_w = int ;
  assign scan_in_w = scan_in ;
  assign scan_en_w = scan_en ;
  assign scan_mode_w = scan_mode ;

  risc8 U0 (
             .cycle (cycle ),
             .write (write ),
             .ifetch (ifetch ),
             .iack (iack ),
             .ie (ie ),
             .address (address ),
             .data_out (data_out ),
             .scan_out (scan_out ),
             .clk (clk_w ),
             .rst_n (rst_n_w ),
             .nmi (nmi_w ),
             .int (int_w ),
             .ready (ready_w ),
             .data_in (data_in_w ),
             .scan_in (scan_in_w ),
             .scan_en (scan_en_w ),
             .scan_en (scan_mode_w )
              );

  initial begin
    $vcdpluson;
  end

  // Clock Generation
  parameter c = 10;
  always begin clk = 1'b0; #(0.5*c); clk = 1'b1; #(0.5*c); end

  initial begin
    rst_n   = 1'h0;
    data_in = 8'h0;
    scan_in = 1'h0;
    scan_en = 1'h0;
    scan_mode = 1'h0;
    #(1*c);  // To Prevent the memory from getting corrupted on reset unknowns
    $readmemh("test.mem", mem);
    $readmemh("reg.mem", U0.U_regb_biu.reg_file);
  end

  // memory writes
  always @ (posedge clk)
    begin
      if(cycle && write)
        mem[address[15:0]] <= data_out;
    end

  // Interrupt Generation Logic
  always @ (posedge clk or negedge rst_n)
    begin
    if (!rst_n)
      begin
        nmi <= 1'b0;
        int <= 1'b0;
        int_vector <= 8'h01;
      end
    else
      begin
        // nmi
        if(cycle && write && (address == 16'h6780) && (data_out == 8'h55))
          begin
            nmi <= 1'b1; int <= 1'b0;
          end
        else if(cycle && write && (address == 16'h6781) && (data_out == 8'h55))
          begin
             nmi <= 1'b0; int <= 1'b1;
          end
        else if(cycle && write && (address == 16'h6783) && (data_out == 8'h55))
          begin
             nmi <= 1'b1; int <= 1'b1;
          end
        else
          begin
             nmi <= 1'b0; int <= 1'b0;
          end
        if(cycle && write && (address == 16'h6782))
          int_vector <= data_out;
      end
    end
    

  // Wait State Generation Logic
  assign ready_w = (ready_cntrl == 8'h01)? (address == address_d)    : (
                   (ready_cntrl == 8'h02)? (address == address_dd)   : (
                   (ready_cntrl == 8'h03)? (address == address_ddd)  : ( 
                   (ready_cntrl == 8'h04)? (address == address_dddd) : 1'b1)));

  always @ (posedge clk or negedge rst_n)
    begin
    if(!rst_n)
      begin
        address_d    <= 8'h00;
        address_dd   <= 8'h00;
        address_ddd  <= 8'h00;
        address_dddd <= 8'h00;
        `ifdef Wait4 
          ready_cntrl  <= 8'h04;
        `else 
           `ifdef Wait3
               ready_cntrl  <= 8'h03;
            `else 
               `ifdef Wait2
                   ready_cntrl  <= 8'h02;
                `else 
                   `ifdef Wait1
                      ready_cntrl  <= 8'h01;
                   `else
                      ready_cntrl  <= 8'h00;
                    `endif
                `endif
           `endif
        `endif
      end
    else
      begin
        address_d    <= address;
        address_dd   <= address_d;
        address_ddd  <= address_dd;
        address_dddd <= address_ddd;
        if(cycle && write && (address == 16'h6785) && ready_w)
          ready_cntrl <= data_out; 
      end
    end
  

  // Test Pass/Fail check
  always @ (posedge clk)
    begin
    if(cycle && write && (address == 16'hffff) && (data_out == 8'h55))
      begin
      $display(" Test Passed @ %t\n", $time);
      $finish;
      end

    if(cycle && write && (address == 16'h1234) && (data_out == 8'ha2))
      begin
      $display(" Test Failed @ %t\n", $time);
      $finish;
      end
    end

  initial begin
    //Please Enter Your Stimulus here
    #(10 * c);
    rst_n <= 1'b1;
    #(32000 * c);
    $display("%x, %x, %x, %x\n", mem[0], mem[1], mem[2], mem[3]);
    $display(" Timeout.... Test Failed @ %t\n", $time);
    $finish;
  end

endmodule