risc8_dc_compile.scr

这是一篇关于8位RISC CPU设计的文章

/*-----------------------------------------------------------------------------
// Author   : S.Aravindhan
// File     : risc8_dc_compile.scr
// Version  : 1.0
// Abstract : design compiler script for risc8. To invoke:
//            dc_shell -f risc8_dc_compile.scr | tee dc.log
//           
// History:
// ============================================================================
// 02/06/00  arvind  1.0      Initial Release
// ==========================================================================*/

 /* Main parameters */
 /* --------------- */
 power_clock_gating = 0  /* 1 - gating;  0 - no-gating, need power compiler */
 scan_insertion     = 0  /* 1 - scan;    0 - no-scan,   need test compiler  */
 flatten            = 0  /* 1-  flatten; 0 - no flatten                     */

 /* Clock specification */
 /* ------------------- */
 clk_period         = 3.3
 clk_uncertainty    = 0.0
 clk_high           = 0.5 * clk_period

 /* library information */
 /* -------------------- */
 target_library    = "xyz_wccomv.db"
 symbol_library    = "xyz.sdb"
 synthetic_library = {dw01.sldb, dw02.sldb, dw03.sldb, dw06.sldb}
 link_library      = "*" + target_library + synthetic_library
 search_path = search_path + "/libraries/syn" 

 nand_name = "ND2A"
 nand_output_pin = "Z"
 nand_input_pin  = "A"
 min_op_condition = "NOM" 
 max_op_condition = "WCCOM" 
 min_library_name = "xyzlib" 
 max_library_name = "xyzlib" 

 /* create work directory */
 /* --------------------- */ 
 remove_design -all
 sh "rm -rf ./work"
 sh "mkdir ./work"
 define_design_lib work -path ./work

 /* Analyze and elaborate */
 /* --------------------- */ 
 module_list = { \
   risc8_alu \
   risc8_regb_biu \
   risc8_control \
   risc8  }

 foreach (module_name, module_list) {
   analyze -format verilog { \
     ../src/risc8_constants.v \
     ../src/risc8_parameters.v \
     "../src/" + module_name + ".v" }
   }

 if (power_clock_gating == 1) {
   set_clock_gating_style -sequential_cell latch -setup 0 -hold 0 \
      -control_point before -control_signal scan_en 
   elaborate -update -architecture "verilog" -gate_clock risc8 
 } else {
     elaborate -update -architecture "verilog" risc8 
 }

 /* Constraints */
 /* ----------- */
 current_design risc8 

 /* clock */
 create_clock -period clk_period clk -wave {0 clk_high}
 set_clock_uncertainty clk_uncertainty clk
 set_fix_hold clk

 /* input output load */
 set_driving_cell -cell nand_name -library  min_library_name \
                  -pin nand_output_pin {all_inputs()}
 set_drive 0 {clk, rst_n, scan_en}
 load_cell = min_library_name + "/" + nand_name + "/" + nand_input_pin
 load = 8 * load_of(load_cell)
 set_load load {all_outputs()} 

 /* input/output timing */
 set_input_delay  clk_uncertainty  -min -clock clk {all_inputs() - clk}
 set_input_delay  0.85 * clk_period -max -clock clk {all_inputs() - clk}
 set_input_delay  0.80 * clk_period -max -clock clk {ready data_in}
 set_input_delay  0.20 * clk_period -max -clock clk {rst_n}
 set_input_delay  0.10 * clk_period -max -clock clk {scan_in scan_mode scan_en}

 set_output_delay 0 -min -clock clk {all_outputs()}
 set_output_delay 0.85 * clk_period -max -clock clk {all_outputs()}
 set_output_delay 0.15 * clk_period -max -clock clk {scan_out}

 /* Operating condition and wireload */
 set_operating_conditions -min min_op_condition -max max_op_condition \
    -min_library min_library_name -max_library max_library_name 
 set_wire_load_mode top

 check_design >> check_report
 set_fix_multiple_port_nets -feedthroughs -outputs
 link

 if (flatten == 1) {
      ungroup -all -flatten
 }

 set_max_area 0 
 propagate_constraints -all
 set_scan_configuration -style multiplexed_flip_flop -methodology full_scan 
 set_critical_range 0.2 * clk_period  risc8
 uniquify

 /* first pass compile */
 /* ------------------ */
 if (scan_insertion == 1) {
    compile -boundary_optimization -map_effort medium -scan
 } else {
     set_logic_zero {scan_mode}
     compile -boundary_optimization -map_effort medium
 }

 /* second pass incremental compile */
 /* ------------------------------- */
 compile -incremental -map_effort high 
 if (flatten) {
    ungroup -all -flatten
 }

 if (scan_insertion == 1) {
    set_scan_signal test_scan_in -port "scan_in"
    set_scan_signal test_scan_out -port "scan_out"
    set_scan_signal test_scan_enable -port "scan_en"
    create_test_clock clk -period 100 -waveform {45 55}
    check_test > risc8.rep 
    insert_scan -map_effort high 
    check_test >> risc8.rep
    create_test_patterns -output "risc8_scan.vdb"
    report_test -coverage  >> risc8.rep
 }

 /* save and report */
 /* --------------- */
 write -f db -hier -o risc8.db
 write -f verilog -hier -o risc8.vg

 report_constraint -all_violators >> risc8.rep
 report_timing >> risc8.rep
 report_area >> risc8.rep
 report_timing -loops >> risc8.rep
 all_registers -level_sensitive >> risc8.rep
 quit