📄 start_v2.lst
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452 ; <i> Number of active ChipSelect pins
0000 453 _CSPEN EQU 0 ; 0 = No CS pins enabled /Dave/
454 ; 1 = One CS (CS0) pin enabled
455 ; : = :
456 ; 8 = Eight CS (CS0 .. CS7) pins enabled
457 ; 9 - 15 = reserved
458 ; Note: the number of available CS pins depends on the chip used
459 ;
460 ; <q> ARBEN: Enable Bus Arbitration Pins (EBCMOD0.8)
0000 461 _ARBEN EQU 0 ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO /Dave/
462 ; 1 = HOLD, HLDA and BREQ pins act normally
463 ;
464 ; <o> SLAVE: SLAVE mode enable (EBCMOD0.9)
465 ; <0=> Master Mode <1=> Slave Mode
0000 466 _SLAVE EQU 0 ; 0 = Bus arbiter acts in master mode /Dave/
467 ; 1 = Bus arbiter acts in slave mode
468 ;
469 ; <q> EBCDIS: Disable EBC pins (EBCMOD0.10)
0001 470 _EBCDIS EQU 1 ; 0 = EBC is using the pins for external bus /Dave/
471 ; 1 = EBC off (pins to be used as GPIO if implemented)
472 ;
473 ; <o> WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
474 ; <0=> WR and BHE <1=> WRL and WRH
0000 475 _WRCFG EQU 0 ; 0 = Pins act as WR and BHE /Dave/
476 ; 1 = Pins act as WRL and WRH
477 ;
478 ; <q> BYTDIS: Disable BHE pin (EBCMOD0.12)
0001 479 _BYTDIS EQU 1 ; 0 = BHE enabled /Dave/
480 ; 1 = BHE disabled (GPIO function if implemented)
481 ;
482 ; <q> ALEDIS: Disable ALE pin (EBCMOD0.13)
0001 483 _ALEDIS EQU 1 ; 0 = ALE pin enabled /Dave/
484 ; 1 = ALE pin disabled (GPIO function if implemented)
485 ;
486 ; <q> RDYDIS: Disable READY pin (EBCMOD0.14)
0001 487 _RDYDIS EQU 1 ; 0 = READY enabled /Dave/
488 ; 1 = READY disabled (GPIO function if implemented)
489 ;
490 ; <o> RDYPOL: READY pin polarity (EBCMOD0.15)
491 ; <0=> Active Low <1=> Active High
0000 492 _RDYPOL EQU 0 ; 0 = READY pin is active low /Dave/
493 ; 1 = READY pin is active high
494 ;
495 ;</h>
A166 MACRO ASSEMBLER START_V2 08/28/2006 10:05:41 PAGE 9
496 ;
497 ; <h>Definitions for EBC Mode 1 register EBCMOD1
498 ; ==============================================
499 ;
500 ; <o> APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD1.3) <0-15>
000F 501 _APDIS EQU 15 ; 0 = Address bus pins 15-1 of PORT1 enabled /Dave/
502 ; 1 = Pin A15 disabled, A14-1 enabled
503 ; 2 = Pin A15-A14 disabled, A13-1 enabled
504 ; ...
505 ; 15 = Pins A15-A1 disabled
506 ;
507 ; <q> A0PDIS: Address Bit 0 Pin Disable (EBCMOD1.4)
0000 508 _A0PDIS EQU 0 ; 0 = Address bus pin 0 of PORT1 enabled
509 ; 1 = Address bus pin 0 of PORT1 enabled
510 ;
511 ; <q> ALPDIS: Address Low Pins Disable (EBCMOD1.5)
0001 512 _ALPDIS EQU 1 ; 0 = Address bus pin 7-0 generally enabled /Dave/
513 ; 1 = Address bus pin 7-0 of PORT1 disabled
514 ;
515 ; <q> DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
0001 516 _DHPDIS EQU 1 ; 0 = Data bus pins 15-8 of PORT0 enabled /Dave/
517 ; 1 = Data bus pins 15-8 disabled (used as GPIO)
518 ;
519 ; <q> WRPDIS: WR/WRL Pin Disable (EBCMOD1.7)
0000 520 _WRPDIS EQU 0 ; 0 = WR/WRL pin of Port P20 enabled /Dave/
521 ; 1 = WR/WRL pin of Port P20 disabled
522 ;
523 ;</h></e>
524 ;
525 ; <e> Configure External Bus Behaviour for CS0 area
526 ; =================================================
527 ;
528 ; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
529 $SET (CONFIG_CS0 = 1) ; /Dave/
530 ;
531 ; <h>Definitions for Function Configuration Register FCONCS0
532 ; =======================================================
533 ;
534 ; <q> ENCS0: Enable Chip Select (FCONCS0.0)
0000 535 _ENCS0 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
536 ; 1 = Chip Select 0 enabled
537 ;
538 ; <q> RDYEN0: Ready Enable (FCONCS0.1)
0000 539 _RDYEN0 EQU 0 ; 0 = Access time controlled by TCONCS0.PHE0 /Dave/
540 ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
541 ;
542 ; <o> RDYMOD0: Ready Mode (FCONCS0.2)
543 ; <0=> Asynchronous <1=> Synchronous
0000 544 _RDYMOD0 EQU 0 ; 0 = Asynchronous READY /Dave/
545 ; 1 = Synchronous READY
546 ;
547 ; <o> BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
548 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
549 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0000 550 _BTYP0 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
551 ; 1 = 8 bit Multiplexed bus
552 ; 2 = 16 bit Demultiplexed bus
553 ; 3 = 16 bit Multiplexed bus
554 ; </h>
555 ;
556 ; <h> TCONCS0: Definitions for the Timing Configuration register
557 ; ==============================================================
558 ;
559 ; <o> PHA0: Phase A clock cycles (TCONCS0.0 .. TCONCS0.1) <0-3>
0003 560 _PHA0 EQU 3 ; 0 = 0 clock cycles /Dave/
A166 MACRO ASSEMBLER START_V2 08/28/2006 10:05:41 PAGE 10
561 ; : = :
562 ; 3 = 3 clock cycles
563 ;
564 ; <o> PHB0: Phase B clock cycles (TCONCS0.2) <1-2> <#-1>
0000 565 _PHB0 EQU 0 ; 0 = 1 clock cycle /Dave/
566 ; 1 = 2 clock cycles
567 ;
568 ; <o> PHC0: Phase C clock cycles (TCONCS0.3 .. TCONCS0.4) <0-3>
0000 569 _PHC0 EQU 0 ; 0 = 0 clock cycles /Dave/
570 ; : = :
571 ; 3 = 3 clock cycles
572 ;
573 ; <o> PHD0: Phase D clock cycle (TCONCS0.5) <0-1>
0000 574 _PHD0 EQU 0 ; 0 = 0 clock cycles /Dave/
575 ; 1 = 1 clock cycle
576 ;
577 ; <o> PHE0: Phase E clock cycles (TCONCS0.6 .. TCONCS0.10) <1-32> <#-1>
0009 578 _PHE0 EQU 9 ; 0 = 1 clock cycle /Dave/
579 ; : = :
580 ; 31 = 32 clock cycles
581 ;
582 ; <o> RDPHF0: Phase F read clock cycles (TCONCS0.11 .. TCONCS0.12) <0-3>
0000 583 _RDPHF0 EQU 0 ; 0 = 0 clock cycles /Dave/
584 ; : = :
585 ; 3 = 3 clock cycles
586 ;
587 ; <o> WRPHF0: Phase F write clock cycles (TCONCS0.13 .. TCONCS0.14) <0-3>
0003 588 _WRPHF0 EQU 3 ; 0 = 0 clock cycles /Dave/
589 ; : = :
590 ; 3 = 3 clock cycles
591 ;</h> </e>
592 ;
593 ; <e> Configure External Bus Behaviour for CS1 Area
594 ; =================================================
595 ;
596 ; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
597 $SET (CONFIG_CS1 = 0) ; /Dave/
598 ;
599 ; <h>Definitions for Address Select register ADDRSEL1
600 ; ===================================================
601 ; <o> CS1 Start Address <0x0-0xFFFFFF:0x1000>
0000 602 _ADDR1 EQU 0x0 ; Set CS1# Start Address (default 100000H) /Dave/
603
604 ; <o> CS1 Size in KB
605 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
606 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
607 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
1000 608 _SIZE1 EQU 4*KB ; Set CS1# Size (default 1024*KB = 1*MB) /Dave/
609 ; possible values for _SIZE1 are:
610 ; 4*KB (gives RGSZ1 = 0)
611 ; 8*KB (gives RGSZ1 = 1)
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