📄 cstart.lst
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FF9C +1 611 CC1_T0IC DEFR 0xFF9C ;CAPCOM 1 Timer 0 Interrupt Control Register
FF9C.6 +1 612 CC1_T0IC_IE BIT CC1_T0IC.6
FF9C.7 +1 613 CC1_T0IC_IR BIT CC1_T0IC.7
FF9C.8 +1 614 CC1_T0IC_GPX BIT CC1_T0IC.8
FF9E +1 615 CC1_T1IC DEFR 0xFF9E ;CC Timer 1 Interrupt Control Register
FF9E.6 +1 616 CC1_T1IC_IE BIT CC1_T1IC.6
FF9E.7 +1 617 CC1_T1IC_IR BIT CC1_T1IC.7
FF9E.8 +1 618 CC1_T1IC_GPX BIT CC1_T1IC.8
+1 619
+1 620 ; LONDONCORE
+1 621
FFAC +1 622 TFR DEFR 0xFFAC ;Trap Flag Register
FFAC.2 +1 623 TFR_ILLOPA BIT TFR.2
FFAC.3 +1 624 TFR_PRTFLT BIT TFR.3
FFAC.4 +1 625 TFR_PACER BIT TFR.4
FFAC.7 +1 626 TFR_UNDOPC BIT TFR.7
FFAC.12 +1 627 TFR_SOFTBRK BIT TFR.12
FFAC.13 +1 628 TFR_STKUF BIT TFR.13
FFAC.14 +1 629 TFR_STKOF BIT TFR.14
FFAC.15 +1 630 TFR_NMI BIT TFR.15
+1 631
+1 632 ; MAC
+1 633
F000 +1 634 QX0 DEFR 0xF000 ;Offset Register
F002 +1 635 QX1 DEFR 0xF002 ;Offset Register
F004 +1 636 QR0 DEFR 0xF004 ;Offset Register
F006 +1 637 QR1 DEFR 0xF006 ;Offset Register
+1 638
+1 639 ; PEC
+1 640
FEC0 +1 641 PECC0 DEFR 0xFEC0 ;PEC Channel 0 Control Register
A166 MACRO ASSEMBLER CSTART 12/17/2004 14:33:07 PAGE 11
FEC2 +1 642 PECC1 DEFR 0xFEC2 ;PEC Channel 1 Control Register
FEC4 +1 643 PECC2 DEFR 0xFEC4 ;PEC Channel 2 Control Register
FEC6 +1 644 PECC3 DEFR 0xFEC6 ;PEC Channel 3 Control Register
FEC8 +1 645 PECC4 DEFR 0xFEC8 ;PEC Channel 4 Control Register
FECA +1 646 PECC5 DEFR 0xFECA ;PEC Channel 5 Control Register
FECC +1 647 PECC6 DEFR 0xFECC ;PEC Channel 6 Control Register
FECE +1 648 PECC7 DEFR 0xFECE ;PEC Channel 7 Control Register
FFA8 +1 649 PECISNC DEFR 0xFFA8 ;PEC Interrupt Subnode Control Register
FFA8.0 +1 650 PECISNC_C0IE BIT PECISNC.0
FFA8.1 +1 651 PECISNC_C0IR BIT PECISNC.1
FFA8.2 +1 652 PECISNC_C1IE BIT PECISNC.2
FFA8.3 +1 653 PECISNC_C1IR BIT PECISNC.3
FFA8.4 +1 654 PECISNC_C2IE BIT PECISNC.4
FFA8.5 +1 655 PECISNC_C2IR BIT PECISNC.5
FFA8.6 +1 656 PECISNC_C3IE BIT PECISNC.6
FFA8.7 +1 657 PECISNC_C3IR BIT PECISNC.7
FFA8.8 +1 658 PECISNC_C4IE BIT PECISNC.8
FFA8.9 +1 659 PECISNC_C4IR BIT PECISNC.9
FFA8.10 +1 660 PECISNC_C5IE BIT PECISNC.10
FFA8.11 +1 661 PECISNC_C5IR BIT PECISNC.11
FFA8.12 +1 662 PECISNC_C6IE BIT PECISNC.12
FFA8.13 +1 663 PECISNC_C6IR BIT PECISNC.13
FFA8.14 +1 664 PECISNC_C7IE BIT PECISNC.14
FFA8.15 +1 665 PECISNC_C7IR BIT PECISNC.15
+1 666
+1 667 ; PORT
+1 668
F080 +1 669 POCON0L DEFR 0xF080 ;Port P0L Output Control Register
F082 +1 670 POCON0H DEFR 0xF082 ;Port P0H Output Control Register
F084 +1 671 POCON1L DEFR 0xF084 ;Port P1L Output Control Register
F086 +1 672 POCON1H DEFR 0xF086 ;Port P1H Output Control Register
F08A +1 673 POCON3 DEFR 0xF08A ;Port P3 Output Control Port
F08C +1 674 POCON4 DEFR 0xF08C ;Port P4 Output Control Port
F094 +1 675 POCON9 DEFR 0xF094 ;Port 9 Output Control Register
F0AA +1 676 POCON20 DEFR 0xF0AA ;Dedicated Pin Output Control Register
F100 +1 677 DP0L DEFR 0xF100 ;P0L Direction Control Register
F100.0 +1 678 DP0L_P0 BIT DP0L.0
F100.1 +1 679 DP0L_P1 BIT DP0L.1
F100.2 +1 680 DP0L_P2 BIT DP0L.2
F100.3 +1 681 DP0L_P3 BIT DP0L.3
F100.4 +1 682 DP0L_P4 BIT DP0L.4
F100.5 +1 683 DP0L_P5 BIT DP0L.5
F100.6 +1 684 DP0L_P6 BIT DP0L.6
F100.7 +1 685 DP0L_P7 BIT DP0L.7
F102 +1 686 DP0H DEFR 0xF102 ;P0H Direction Control Register
F102.0 +1 687 DP0H_P0 BIT DP0H.0
F102.1 +1 688 DP0H_P1 BIT DP0H.1
F102.2 +1 689 DP0H_P2 BIT DP0H.2
F102.3 +1 690 DP0H_P3 BIT DP0H.3
F102.4 +1 691 DP0H_P4 BIT DP0H.4
F102.5 +1 692 DP0H_P5 BIT DP0H.5
F102.6 +1 693 DP0H_P6 BIT DP0H.6
F102.7 +1 694 DP0H_P7 BIT DP0H.7
F104 +1 695 DP1L DEFR 0xF104 ;P1L Direction Control Register
F104.0 +1 696 DP1L_P0 BIT DP1L.0
F104.1 +1 697 DP1L_P1 BIT DP1L.1
F104.2 +1 698 DP1L_P2 BIT DP1L.2
F104.3 +1 699 DP1L_P3 BIT DP1L.3
F104.4 +1 700 DP1L_P4 BIT DP1L.4
F104.5 +1 701 DP1L_P5 BIT DP1L.5
F104.6 +1 702 DP1L_P6 BIT DP1L.6
F104.7 +1 703 DP1L_P7 BIT DP1L.7
F106 +1 704 DP1H DEFR 0xF106 ;P1H Direction Control Register
F106.0 +1 705 DP1H_P0 BIT DP1H.0
F106.1 +1 706 DP1H_P1 BIT DP1H.1
F106.2 +1 707 DP1H_P2 BIT DP1H.2
A166 MACRO ASSEMBLER CSTART 12/17/2004 14:33:07 PAGE 12
F106.3 +1 708 DP1H_P3 BIT DP1H.3
F106.4 +1 709 DP1H_P4 BIT DP1H.4
F106.5 +1 710 DP1H_P5 BIT DP1H.5
F106.6 +1 711 DP1H_P6 BIT DP1H.6
F106.7 +1 712 DP1H_P7 BIT DP1H.7
F120 +1 713 ALTSEL0P1H DEFR 0xF120 ;Alternate I/O Source 0 Port P1H
F120.0 +1 714 ALTSEL0P1H_P0 BIT ALTSEL0P1H.0
F120.1 +1 715 ALTSEL0P1H_P1 BIT ALTSEL0P1H.1
F120.2 +1 716 ALTSEL0P1H_P2 BIT ALTSEL0P1H.2
F120.3 +1 717 ALTSEL0P1H_P3 BIT ALTSEL0P1H.3
F120.4 +1 718 ALTSEL0P1H_P4 BIT ALTSEL0P1H.4
F120.5 +1 719 ALTSEL0P1H_P5 BIT ALTSEL0P1H.5
F120.6 +1 720 ALTSEL0P1H_P6 BIT ALTSEL0P1H.6
F120.7 +1 721 ALTSEL0P1H_P7 BIT ALTSEL0P1H.7
F126 +1 722 ALTSEL0P3 DEFR 0xF126 ;Alternate I/O Source Port 3 Selection
F126.1 +1 723 ALTSEL0P3_P1 BIT ALTSEL0P3.1
F126.3 +1 724 ALTSEL0P3_P3 BIT ALTSEL0P3.3
F126.8 +1 725 ALTSEL0P3_P8 BIT ALTSEL0P3.8
F126.9 +1 726 ALTSEL0P3_P9 BIT ALTSEL0P3.9
F126.10 +1 727 ALTSEL0P3_P10 BIT ALTSEL0P3.10
F126.11 +1 728 ALTSEL0P3_P11 BIT ALTSEL0P3.11
F126.13 +1 729 ALTSEL0P3_P13 BIT ALTSEL0P3.13
F128 +1 730 ALTSEL1P3 DEFR 0xF128 ;Alternate I/O Source 1 Port P3
F128.1 +1 731 ALTSEL1P3_P1 BIT ALTSEL1P3.1
F12A +1 732 ALTSEL0P4 DEFR 0xF12A ;Alternate I/O Source 0 Port P4
F12A.6 +1 733 ALTSEL0P4_P6 BIT ALTSEL0P4.6
F12A.7 +1 734 ALTSEL0P4_P7 BIT ALTSEL0P4.7
F130 +1 735 ALTSEL0P1L DEFR 0xF130 ;P1L Alternate Select Register 0
F130.0 +1 736 ALTSEL0P1L_P0 BIT ALTSEL0P1L.0
F130.1 +1 737 ALTSEL0P1L_P1 BIT ALTSEL0P1L.1
F130.2 +1 738 ALTSEL0P1L_P2 BIT ALTSEL0P1L.2
F130.3 +1 739 ALTSEL0P1L_P3 BIT ALTSEL0P1L.3
F130.4 +1 740 ALTSEL0P1L_P4 BIT ALTSEL0P1L.4
F130.5 +1 741 ALTSEL0P1L_P5 BIT ALTSEL0P1L.5
F130.6 +1 742 ALTSEL0P1L_P6 BIT ALTSEL0P1L.6
F130.7 +1 743 ALTSEL0P1L_P7 BIT ALTSEL0P1L.7
F136 +1 744 ALTSEL1P4 DEFR 0xF136 ;Alternate I/O Source 1 Port P4
F136.7 +1 745 ALTSEL1P4_P7 BIT ALTSEL1P4.7
F138 +1 746 ALTSEL0P9 DEFR 0xF138 ;Alternate I/O Source 0 Port P9
F138.0 +1 747 ALTSEL0P9_P0 BIT ALTSEL0P9.0
F138.1 +1 748 ALTSEL0P9_P1 BIT ALTSEL0P9.1
F138.2 +1 749 ALTSEL0P9_P2 BIT ALTSEL0P9.2
F138.3 +1 750 ALTSEL0P9_P3 BIT ALTSEL0P9.3
F138.4 +1 751 ALTSEL0P9_P4 BIT ALTSEL0P9.4
F138.5 +1 752 ALTSEL0P9_P5 BIT ALTSEL0P9.5
F13A +1 753 ALTSEL1P9 DEFR 0xF13A ;Alternate I/O Source 1 Port P9
F13A.0 +1 754 ALTSEL1P9_P0 BIT ALTSEL1P9.0
F13A.1 +1 755 ALTSEL1P9_P1 BIT ALTSEL1P9.1
F13A.2 +1 756 ALTSEL1P9_P2 BIT ALTSEL1P9.2
F13A.3 +1 757 ALTSEL1P9_P3 BIT ALTSEL1P9.3
F13A.4 +1 758 ALTSEL1P9_P4 BIT ALTSEL1P9.4
F13A.5 +1 759 ALTSEL1P9_P5 BIT ALTSEL1P9.5
F1C4 +1 760 PICON DEFR 0xF1C4 ;Port Input Control Register
F1C4.2 +1 761 PICON_P3LIN BIT PICON.2
F1C4.3 +1 762 PICON_P3HIN BIT PICON.3
F1C4.4 +1 763 PICON_P4LIN BIT PICON.4
F1C4.7 +1 764 PICON_P9LIN BIT PICON.7
F1C4.8 +1 765 PICON_P20LIN BIT PICON.8
F1C4.9 +1 766⌨️ 快捷键说明
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