📄 cstart.lst
字号:
FF5C.7 +1 143 CC1_OUT_CC7IO BIT CC1_OUT.7
FF5C.8 +1 144 CC1_OUT_CC8IO BIT CC1_OUT.8
FF5C.9 +1 145 CC1_OUT_CC9IO BIT CC1_OUT.9
FF5C.10 +1 146 CC1_OUT_CC10IO BIT CC1_OUT.10
FF5C.11 +1 147 CC1_OUT_CC11IO BIT CC1_OUT.11
FF5C.12 +1 148 CC1_OUT_CC12IO BIT CC1_OUT.12
FF5C.13 +1 149 CC1_OUT_CC13IO BIT CC1_OUT.13
FF5C.14 +1 150 CC1_OUT_CC14IO BIT CC1_OUT.14
FF5C.15 +1 151 CC1_OUT_CC15IO BIT CC1_OUT.15
FFEC +1 152 CC1_ID EQU 0xFFEC ;CAPCOM1 Module Identification Register
+1 153
+1 154 ; CC2
+1 155
F050 +1 156 CC2_T7 DEFR 0xF050 ;CAPCOM 2 Timer 7 Register
F052 +1 157 CC2_T8 DEFR 0xF052 ;CAPCOM 2 Timer 8 Register
F054 +1 158 CC2_T7REL DEFR 0xF054 ;CAPCOM 2 Timer 7 Reload Register
F056 +1 159 CC2_T8REL DEFR 0xF056 ;CAPCOM 2 Timer 8 Reload Register
F066 +1 160 CC2_IOC DEFR 0xF066 ;CAPCOM2 IO Control
FE28 +1 161 CC2_SEM DEFR 0xFE28 ;CAPCOM 2 Single Event Control Register
FE2A +1 162 CC2_SEE DEFR 0xFE2A ;CAPCOM 2 Single Event Enable Register
FE60 +1 163 CC2_CC16 DEFR 0xFE60 ;CAPCOM 2 Register 16
FE62 +1 164 CC2_CC17 DEFR 0xFE62 ;CAPCOM 2 Register 17
FE64 +1 165 CC2_CC18 DEFR 0xFE64 ;CAPCOM 2 Register 18
FE66 +1 166 CC2_CC19 DEFR 0xFE66 ;CAPCOM 2 Register 19
FE68 +1 167 CC2_CC20 DEFR 0xFE68 ;CAPCOM 2 Register 20
FE6A +1 168 CC2_CC21 DEFR 0xFE6A ;CAPCOM 2 Register 21
FE6C +1 169 CC2_CC22 DEFR 0xFE6C ;CAPCOM 2 Register 22
FE6E +1 170 CC2_CC23 DEFR 0xFE6E ;CAPCOM 2 Register 23
FE70 +1 171 CC2_CC24 DEFR 0xFE70 ;CAPCOM 2 Register 24
FE72 +1 172 CC2_CC25 DEFR 0xFE72 ;CAPCOM 2 Register 25
FE74 +1 173 CC2_CC26 DEFR 0xFE74 ;CAPCOM 2 Register 26
FE76 +1 174 CC2_CC27 DEFR 0xFE76 ;CAPCOM 2 Register 27
FE78 +1 175 CC2_CC28 DEFR 0xFE78 ;CAPCOM 2 Register 28
FE7A +1 176 CC2_CC29 DEFR 0xFE7A ;CAPCOM 2 Register 29
FE7C +1 177 CC2_CC30 DEFR 0xFE7C ;CAPCOM 2 Register 30
FE7E +1 178 CC2_CC31 DEFR 0xFE7E ;CAPCOM 2 Register 31
FF20 +1 179 CC2_T78CON DEFR 0xFF20 ;CAPCOM 2 Timer 7 and Timer 8 Control Registe
r
FF20.3 +1 180 CC2_T78CON_T7M BIT CC2_T78CON.3
FF20.6 +1 181 CC2_T78CON_T7R BIT CC2_T78CON.6
FF20.11 +1 182 CC2_T78CON_T8M BIT CC2_T78CON.11
A166 MACRO ASSEMBLER CSTART 12/17/2004 14:33:07 PAGE 4
FF20.14 +1 183 CC2_T78CON_T8R BIT CC2_T78CON.14
FF22 +1 184 CC2_M4 DEFR 0xFF22 ;CC Mode Control Register 4
FF22.3 +1 185 CC2_M4_ACC16 BIT CC2_M4.3
FF22.7 +1 186 CC2_M4_ACC17 BIT CC2_M4.7
FF22.11 +1 187 CC2_M4_ACC18 BIT CC2_M4.11
FF22.15 +1 188 CC2_M4_ACC19 BIT CC2_M4.15
FF24 +1 189 CC2_M5 DEFR 0xFF24 ;CC Mode Control Register 5
FF24.3 +1 190 CC2_M5_ACC20 BIT CC2_M5.3
FF24.7 +1 191 CC2_M5_ACC21 BIT CC2_M5.7
FF24.11 +1 192 CC2_M5_ACC22 BIT CC2_M5.11
FF24.15 +1 193 CC2_M5_ACC23 BIT CC2_M5.15
FF26 +1 194 CC2_M6 DEFR 0xFF26 ;CC Mode Control Register 6
FF26.3 +1 195 CC2_M6_ACC24 BIT CC2_M6.3
FF26.7 +1 196 CC2_M6_ACC25 BIT CC2_M6.7
FF26.11 +1 197 CC2_M6_ACC26 BIT CC2_M6.11
FF26.15 +1 198 CC2_M6_ACC27 BIT CC2_M6.15
FF28 +1 199 CC2_M7 DEFR 0xFF28 ;CC Mode Control Register 7
FF28.3 +1 200 CC2_M7_ACC28 BIT CC2_M7.3
FF28.7 +1 201 CC2_M7_ACC29 BIT CC2_M7.7
FF28.11 +1 202 CC2_M7_ACC30 BIT CC2_M7.11
FF28.15 +1 203 CC2_M7_ACC31 BIT CC2_M7.15
FF2A +1 204 CC2_DRM DEFR 0xFF2A ;CAPCOM 2 Double Register Mode Register
FF2C +1 205 CC2_OUT DEFR 0xFF2C ;CAPCOM 2 Output Register
FF2C.0 +1 206 CC2_OUT_CC0IO BIT CC2_OUT.0
FF2C.1 +1 207 CC2_OUT_CC1IO BIT CC2_OUT.1
FF2C.2 +1 208 CC2_OUT_CC2IO BIT CC2_OUT.2
FF2C.3 +1 209 CC2_OUT_CC3IO BIT CC2_OUT.3
FF2C.4 +1 210 CC2_OUT_CC4IO BIT CC2_OUT.4
FF2C.5 +1 211 CC2_OUT_CC5IO BIT CC2_OUT.5
FF2C.6 +1 212 CC2_OUT_CC6IO BIT CC2_OUT.6
FF2C.7 +1 213 CC2_OUT_CC7IO BIT CC2_OUT.7
FF2C.8 +1 214 CC2_OUT_CC8IO BIT CC2_OUT.8
FF2C.9 +1 215 CC2_OUT_CC9IO BIT CC2_OUT.9
FF2C.10 +1 216 CC2_OUT_CC10IO BIT CC2_OUT.10
FF2C.11 +1 217 CC2_OUT_CC11IO BIT CC2_OUT.11
FF2C.12 +1 218 CC2_OUT_CC12IO BIT CC2_OUT.12
FF2C.13 +1 219 CC2_OUT_CC13IO BIT CC2_OUT.13
FF2C.14 +1 220 CC2_OUT_CC14IO BIT CC2_OUT.14
FF2C.15 +1 221 CC2_OUT_CC15IO BIT CC2_OUT.15
FFEE +1 222 CC2_ID EQU 0xFFEE ;CAPCOM2 Module Identification Register
+1 223
+1 224 ; CERBERUS
+1 225
F068 +1 226 COMDATA DEFR 0xF068 ;Communication Mode data register
+1 227
+1 228 ; CORE
+1 229
F00C +1 230 CPUID DEFR 0xF00C ;CPU Identification Register
FE00 +1 231 DPP0 DEFR 0xFE00 ;CPU Data Page Pointer 0 Register
FE02 +1 232 DPP1 DEFR 0xFE02 ;CPU Data Page Pointer 1 Register
FE04 +1 233 DPP2 DEFR 0xFE04 ;CPU Data Page Pointer 2 Register
FE06 +1 234 DPP3 DEFR 0xFE06 ;CPU Data Page Pointer 3 Register
FE08 +1 235 CSP DEFR 0xFE08 ;CPU Code Segment Pointer Register
FE0C +1 236 MDH DEFR 0xFE0C ;CPU Multiply Divide Register - High Word
FE0E +1 237 MDL DEFR 0xFE0E ;CPU Multiply Divide Register - Low Word
FE10 +1 238 CP DEFR 0xFE10 ;CPU Context Pointer Register
FE12 +1 239 SP DEFR 0xFE12 ;CPU System Stack Pointer Register
FE14 +1 240 STKOV DEFR 0xFE14 ;CPU Stack Overflow Pointer Register
FE16 +1 241 STKUN DEFR 0xFE16 ;CPU Stack Underflow Pointer Register
FE18 +1 242 CPUCON1 DEFR 0xFE18 ;CPU Control Register 1
FE1A +1 243 CPUCON2 DEFR 0xFE1A ;CPU Control Register 2
FE5C +1 244 MAL DEFR 0xFE5C ;Accumulator Low Word
FE5E +1 245 MAH DEFR 0xFE5E ;Accumulator High Word
FF08 +1 246 IDX0 DEFR 0xFF08 ;Address Pointer
FF0A +1 247 IDX1 DEFR 0xFF0A ;Address Pointer
FF0C +1 248 SPSEG DEFR 0xFF0C ;Stack Pointer Segment Register
A166 MACRO ASSEMBLER CSTART 12/17/2004 14:33:07 PAGE 5
FF0E +1 249 MDC DEFR 0xFF0E ;CPU Multiply Divide Control Register
FF0E.4 +1 250 MDC_MDRIU BIT MDC.4
FF10 +1 251 PSW DEFR 0xFF10 ;Processor Status Word
FF10.0 +1 252 PSW_N BIT PSW.0
FF10.1 +1 253 PSW_C BIT PSW.1
FF10.2 +1 254 PSW_V BIT PSW.2
FF10.3 +1 255 PSW_Z BIT PSW.3
FF10.4 +1 256 PSW_E BIT PSW.4
FF10.5 +1 257 PSW_MULIP BIT PSW.5
FF10.6 +1 258 PSW_USR0 BIT PSW.6
FF10.7 +1 259 PSW_USR1 BIT PSW.7
FF10.10 +1 260 PSW_S1 BIT PSW.10
FF10.11 +1 261 PSW_IEN BIT PSW.11
FF12 +1 262 VECSEG DEFR 0xFF12 ;Vector Segment Pointer
FF1C +1 263 ZEROS DEFR 0xFF1C ;Constant Value 0's Register
FF1E +1 264 ONES DEFR 0xFF1E ;Constant Value 1's Register
FFDA +1 265 MRW DEFR 0xFFDA ;MAC Repeat Word
FFDC +1 266 MCW DEFR 0xFFDC ;MAC Control Word
FFDC.9 +1 267 MCW_MS BIT MCW.9
FFDC.10 +1 268 MCW_MP BIT MCW.10
FFDE +1 269 MSW DEFR 0xFFDE ;MAC Unit Status Word
FFDE.8 +1 270 MSW_MN BIT MSW.8
FFDE.9 +1 271 MSW_MZ BIT MSW.9
FFDE.10 +1 272 MSW_MC BIT MSW.10
FFDE.11 +1 273 MSW_MSV BIT MSW.11
FFDE.12 +1 274 MSW_ME BIT MSW.12
FFDE.13 +1 275 MSW_MSL BIT MSW.13
FFDE.14 +1 276 MSW_MV BIT MSW.14
+1 277
+1 278 ; GPT12
+1 279
FE40 +1 280 GPT12E_T2 DEFR 0xFE40 ;GPT1 Timer 2 Register
FE42 +1 281 GPT12E_T3 DEFR 0xFE42 ;GPT1 Timer 3 Register
FE44 +1 282 GPT12E_T4 DEFR 0xFE44 ;GPT1 Timer 4 Register
FE46 +1 283 GPT12E_T5 DEFR 0xFE46 ;GPT2 Timer 5 Register
FE48 +1 284 GPT12E_T6 DEFR 0xFE48 ;GPT2 Timer 6 Register
FE4A +1 285 GPT12E_CAPREL DEFR 0xFE4A ;GPT12 Capture/Reload Register
FF40 +1 286 GPT12E_T2CON DEFR 0xFF40 ;GPT1 Timer 2 Control Register
FF40.6 +1 287 GPT12E_T2CON_T2R BIT GPT12E_T2CON.6
FF40.7 +1 288 GPT12E_T2CON_T2UD BIT GPT12E_T2CON.7
FF40.8 +1 289 GPT12E_T2CON_T2UDE BIT GPT12E_T2CON.8
FF40.9 +1 290 GPT12E_T2CON_T2RC BIT GPT12E_T2CON.9
FF40.12 +1 291 GPT12E_T2CON_T2IRDIS BIT GPT12E_T2CON.12
FF40.13 +1 292 GPT12E_T2CON_T2EDGE BIT GPT12E_T2CON.13
FF40.14 +1 293 GPT12E_T2CON_T2CHDIR BIT GPT12E_T2CON.14
FF40.15 +1 294 GPT12E_T2CON_T2RDIR BIT GPT12E_T2CON.15
FF42 +1 295 GPT12E_T3CON DEFR 0xFF42 ;GPT1 Timer 3 Control Register
FF42.6 +1 296 GPT12E_T3CON_T3R BIT GPT12E_T3CON.6
FF42.7 +1 297 GPT12E_T3CON_T3UD BIT GPT12E_T3CON.7
FF42.8 +1 298 GPT12E_T3CON_T3UDE BIT GPT12E_T3CON.8
FF42.9 +1 299 GPT12E_T3CON_T3OE BIT GPT12E_T3CON.9
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -