📄 cstart.lst
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A166 MACRO ASSEMBLER CSTART 12/17/2004 14:33:07 PAGE 1
MACRO ASSEMBLER A166 V5.00
OBJECT MODULE PLACED IN cstart.OBJ
ASSEMBLER INVOKED BY: C:\Keil\C166\BIN\A166.EXE cstart.asm MODV2 SEGMENTED MODV2 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ; shrinked 'cstartx2.asm' by U. Kelling
2
3 $CASE
4 $GENONLY
5 $DEBUG
6 ;$NOLOCALS
7 ;$CHECKCPU16
8 ;$CHECKBUS18
9 $NOMOD166
10 ;$EXTEND2
11 ;$MODEL(SMALL)
12 ;$STDNAMES(regXC161CJ.DEF)
13
14 $include (xc164.inc)
+1 15 ;--------------------------------------------------------------------------
+1 16 ;REGXC164CS-16FF.inc
+1 17 ;Register Declarations for XC164CS-16FF Processor
+1 18 ;Copyright (c) 1994-1999 Keil Elektronik GmbH and Keil Software, Inc.
+1 19 ;All rights reserved. Rev 2001-04-11
+1 20 ;--------------------------------------------------------------------------
+1 21
+1 22 ; ADC
+1 23
F09C +1 24 ADC_CTR2 DEFR 0xF09C ;A/D Converter Control Register 2
F09E +1 25 ADC_CTR2IN DEFR 0xF09E ;A/D Converter Injection Control Register 2
F0A0 +1 26 ADC_DAT2 DEFR 0xF0A0 ;A/D Converter Result Register 2
FEA0 +1 27 ADC_DAT DEFR 0xFEA0 ;A/D Converter Result Register
FEA8 +1 28 ADC_ID DEFR 0xFEA8 ;A/D Converter ID Register
FFA0 +1 29 ADC_CON DEFR 0xFFA0 ;A/D Converter Control Register
FFA0.7 +1 30 ADC_CON_ADST BIT ADC_CON.7
FFA0.8 +1 31 ADC_CON_ADBSY BIT ADC_CON.8
FFA0.9 +1 32 ADC_CON_ADWR BIT ADC_CON.9
FFA0.10 +1 33 ADC_CON_ADCIN BIT ADC_CON.10
FFA0.11 +1 34 ADC_CON_ADCRQ BIT ADC_CON.11
FFA6 +1 35 ADC_CON1 DEFR 0xFFA6 ;A/D Converter Control Register 1
FFA6.12 +1 36 ADC_CON1_RES BIT ADC_CON1.12
FFA6.13 +1 37 ADC_CON1_CAL BIT ADC_CON1.13
FFA6.14 +1 38 ADC_CON1_SAMPLE BIT ADC_CON1.14
FFA6.15 +1 39 ADC_CON1_ICST BIT ADC_CON1.15
FFBE +1 40 ADC_CTR0 DEFR 0xFFBE ;A/D Converter Control Register 0
FFBE.7 +1 41 ADC_CTR0_ADST BIT ADC_CTR0.7
FFBE.8 +1 42 ADC_CTR0_ADBSY BIT ADC_CTR0.8
FFBE.9 +1 43 ADC_CTR0_ADWR BIT ADC_CTR0.9
FFBE.10 +1 44 ADC_CTR0_ADCIN BIT ADC_CTR0.10
FFBE.11 +1 45 ADC_CTR0_ADCRQ BIT ADC_CTR0.11
FFBE.14 +1 46 ADC_CTR0_SAMPLE BIT ADC_CTR0.14
FFBE.15 +1 47 ADC_CTR0_MD BIT ADC_CTR0.15
+1 48
+1 49 ; ASC0
+1 50
F0B8 +1 51 ASC0_ABSTAT DEFR 0xF0B8 ;ASC0 Autobaud Status Register
F0BA +1 52 ASC0_FSTAT DEFR 0xF0BA ;FIFO Status Register
F0C4 +1 53 ASC0_TXFCON DEFR 0xF0C4 ;Transmit FIFO Control Register
F0C6 +1 54 ASC0_RXFCON DEFR 0xF0C6 ;Receive FIFO Control Register
F1B8 +1 55 ASC0_ABCON DEFR 0xF1B8 ;ASC0 Autobaud Control Register
F1B8.0 +1 56 ASC0_ABCON_ABEN BIT ASC0_ABCON.0
F1B8.1 +1 57 ASC0_ABCON_AUREN BIT ASC0_ABCON.1
F1B8.2 +1 58 ASC0_ABCON_ABSTEN BIT ASC0_ABCON.2
A166 MACRO ASSEMBLER CSTART 12/17/2004 14:33:07 PAGE 2
F1B8.3 +1 59 ASC0_ABCON_ABDETEN BIT ASC0_ABCON.3
F1B8.4 +1 60 ASC0_ABCON_FCDETEN BIT ASC0_ABCON.4
F1B8.10 +1 61 ASC0_ABCON_TXINV BIT ASC0_ABCON.10
F1B8.11 +1 62 ASC0_ABCON_RXINV BIT ASC0_ABCON.11
FEAA +1 63 ASC0_PMW DEFR 0xFEAA ;ASC0 IrDA Pulse Mode and Width Reg.
FEB0 +1 64 ASC0_TBUF DEFR 0xFEB0 ;Serial Channel 0 Transmitter Buffer Register
(WO)
FEB2 +1 65 ASC0_RBUF DEFR 0xFEB2 ;Serial Channel 0 Receiver Buffer Register (R
O)
FEB4 +1 66 ASC0_BG DEFR 0xFEB4 ;Serial Channel 0 Baud Rate Generator Reload
Register
FEB6 +1 67 ASC0_FDV DEFR 0xFEB6 ;Fractional Divider Register
FFB0 +1 68 ASC0_CON DEFR 0xFFB0 ;Serial Channel 0 Control Register
FFB0.3 +1 69 ASC0_CON_STP BIT ASC0_CON.3
FFB0.4 +1 70 ASC0_CON_REN BIT ASC0_CON.4
FFB0.5 +1 71 ASC0_CON_PEN_RXDI BIT ASC0_CON.5
FFB0.6 +1 72 ASC0_CON_FEN BIT ASC0_CON.6
FFB0.7 +1 73 ASC0_CON_OEN BIT ASC0_CON.7
FFB0.8 +1 74 ASC0_CON_PE BIT ASC0_CON.8
FFB0.9 +1 75 ASC0_CON_FE BIT ASC0_CON.9
FFB0.10 +1 76 ASC0_CON_OE BIT ASC0_CON.10
FFB0.11 +1 77 ASC0_CON_S0FDE BIT ASC0_CON.11
FFB0.12 +1 78 ASC0_CON_ODD BIT ASC0_CON.12
FFB0.13 +1 79 ASC0_CON_BRS BIT ASC0_CON.13
FFB0.14 +1 80 ASC0_CON_LB BIT ASC0_CON.14
FFB0.15 +1 81 ASC0_CON_R BIT ASC0_CON.15
FFE2 +1 82 ASC0_ID EQU 0xFFE2 ;ASC0 Identification Register
+1 83
+1 84 ; CC1
+1 85
F062 +1 86 CC1_IOC DEFR 0xF062 ;CAPCOM1 IO Control
FE2C +1 87 CC1_SEM DEFR 0xFE2C ;CAPCOM 1 Single Event Control Register
FE2E +1 88 CC1_SEE DEFR 0xFE2E ;CAPCOM 1 Single Event Enable Register
FE50 +1 89 CC1_T0 DEFR 0xFE50 ;CAPCOM 1 Timer 0 Register
FE52 +1 90 CC1_T1 DEFR 0xFE52 ;CAPCOM 1 Timer 1 Register
FE54 +1 91 CC1_T0REL DEFR 0xFE54 ;CAPCOM 1 Timer 0 Reload Register
FE56 +1 92 CC1_T1REL DEFR 0xFE56 ;CC Timer 1 Reloed Register
FE80 +1 93 CC1_CC0 DEFR 0xFE80 ;CAPCOM 1 Register 0
FE82 +1 94 CC1_CC1 DEFR 0xFE82 ;CAPCOM 1 Register 1
FE84 +1 95 CC1_CC2 DEFR 0xFE84 ;CAPCOM 1 Register 2
FE86 +1 96 CC1_CC3 DEFR 0xFE86 ;CAPCOM 1 Register 3
FE88 +1 97 CC1_CC4 DEFR 0xFE88 ;CAPCOM 1 Register 4
FE8A +1 98 CC1_CC5 DEFR 0xFE8A ;CAPCOM 1 Register 5
FE8C +1 99 CC1_CC6 DEFR 0xFE8C ;CAPCOM 1 Register 6
FE8E +1 100 CC1_CC7 DEFR 0xFE8E ;CAPCOM 1 Register 7
FE90 +1 101 CC1_CC8 DEFR 0xFE90 ;CAPCOM 1 Register 8
FE92 +1 102 CC1_CC9 DEFR 0xFE92 ;CAPCOM 1 Register 9
FE94 +1 103 CC1_CC10 DEFR 0xFE94 ;CAPCOM 1 Register 10
FE96 +1 104 CC1_CC11 DEFR 0xFE96 ;CAPCOM 1 Register 11
FE98 +1 105 CC1_CC12 DEFR 0xFE98 ;CAPCOM 1 Register 12
FE9A +1 106 CC1_CC13 DEFR 0xFE9A ;CAPCOM 1 Register 13
FE9C +1 107 CC1_CC14 DEFR 0xFE9C ;CAPCOM 1 Register 14
FE9E +1 108 CC1_CC15 DEFR 0xFE9E ;CAPCOM 1 Register 15
FF50 +1 109 CC1_T01CON DEFR 0xFF50 ;Timer 0/1 Control Register
FF50.3 +1 110 CC1_T01CON_T0M BIT CC1_T01CON.3
FF50.6 +1 111 CC1_T01CON_T0R BIT CC1_T01CON.6
FF50.11 +1 112 CC1_T01CON_T1M BIT CC1_T01CON.11
FF50.14 +1 113 CC1_T01CON_T1R BIT CC1_T01CON.14
FF52 +1 114 CC1_M0 DEFR 0xFF52 ;Capture/Compare Mode Registers for the CAPCO
M Unit (CC0...CC3)
FF52.3 +1 115 CC1_M0_ACC0 BIT CC1_M0.3
FF52.7 +1 116 CC1_M0_ACC1 BIT CC1_M0.7
FF52.11 +1 117 CC1_M0_ACC2 BIT CC1_M0.11
FF52.15 +1 118 CC1_M0_ACC3 BIT CC1_M0.15
FF54 +1 119 CC1_M1 DEFR 0xFF54 ;Capture/Compare Mode Register for the CAPCOM
Unit (CC4...CC79
A166 MACRO ASSEMBLER CSTART 12/17/2004 14:33:07 PAGE 3
FF54.3 +1 120 CC1_M1_ACC4 BIT CC1_M1.3
FF54.7 +1 121 CC1_M1_ACC5 BIT CC1_M1.7
FF54.11 +1 122 CC1_M1_ACC6 BIT CC1_M1.11
FF54.15 +1 123 CC1_M1_ACC7 BIT CC1_M1.15
FF56 +1 124 CC1_M2 DEFR 0xFF56 ;Capture/Compare Mode Registers for the CAPCO
M Unit (CC8...CC11)
FF56.3 +1 125 CC1_M2_ACC8 BIT CC1_M2.3
FF56.7 +1 126 CC1_M2_ACC9 BIT CC1_M2.7
FF56.11 +1 127 CC1_M2_ACC10 BIT CC1_M2.11
FF56.15 +1 128 CC1_M2_ACC11 BIT CC1_M2.15
FF58 +1 129 CC1_M3 DEFR 0xFF58 ;Capture/Compare Mode Registers for the CAPCO
M Unit (CC12...CC15)
FF58.3 +1 130 CC1_M3_ACC12 BIT CC1_M3.3
FF58.7 +1 131 CC1_M3_ACC13 BIT CC1_M3.7
FF58.11 +1 132 CC1_M3_ACC14 BIT CC1_M3.11
FF58.15 +1 133 CC1_M3_ACC15 BIT CC1_M3.15
FF5A +1 134 CC1_DRM DEFR 0xFF5A ;CAPCOM1 Double Register Mode Register
FF5C +1 135 CC1_OUT DEFR 0xFF5C ;CAPCOM1 Output Register
FF5C.0 +1 136 CC1_OUT_CC0IO BIT CC1_OUT.0
FF5C.1 +1 137 CC1_OUT_CC1IO BIT CC1_OUT.1
FF5C.2 +1 138 CC1_OUT_CC2IO BIT CC1_OUT.2
FF5C.3 +1 139 CC1_OUT_CC3IO BIT CC1_OUT.3
FF5C.4 +1 140 CC1_OUT_CC4IO BIT CC1_OUT.4
FF5C.5 +1 141 CC1_OUT_CC5IO BIT CC1_OUT.5
FF5C.6 +1 142 CC1_OUT_CC6IO BIT CC1_OUT.6
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