gt96132reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#define SDMA_G1_CHAN3_CONFIG_REG        0x130900
#define SDMA_G1_CHAN3_COMM_REG          0x130908
#define SDMA_G1_CHAN3_RX_DESC_BASE      0x138900 
#define SDMA_G1_CHAN3_CURR_RX_DESC_PTR  0x138910
#define SDMA_G1_CHAN3_TX_DESC_BASE      0x13C900 
#define SDMA_G1_CHAN3_CURR_TX_DESC_PTR  0x13C910
#define SDMA_G1_CHAN3_1ST_TX_DESC_PTR   0x13C914
#define SDMA_G1_CHAN4_CONFIG_REG        0x140900
#define SDMA_G1_CHAN4_COMM_REG          0x140908
#define SDMA_G1_CHAN4_RX_DESC_BASE      0x148900 
#define SDMA_G1_CHAN4_CURR_RX_DESC_PTR  0x148910
#define SDMA_G1_CHAN4_TX_DESC_BASE      0x14C900 
#define SDMA_G1_CHAN4_CURR_TX_DESC_PTR  0x14C910
#define SDMA_G1_CHAN4_1ST_TX_DESC_PTR   0x14C914
#define SDMA_G1_CHAN5_CONFIG_REG        0x150900
#define SDMA_G1_CHAN5_COMM_REG          0x150908
#define SDMA_G1_CHAN5_RX_DESC_BASE      0x158900 
#define SDMA_G1_CHAN5_CURR_RX_DESC_PTR  0x158910
#define SDMA_G1_CHAN5_TX_DESC_BASE      0x15C900 
#define SDMA_G1_CHAN5_CURR_TX_DESC_PTR  0x15C910
#define SDMA_G1_CHAN5_1ST_TX_DESC_PTR   0x15C914
#define SDMA_G1_CHAN6_CONFIG_REG        0x160900
#define SDMA_G1_CHAN6_COMM_REG          0x160908
#define SDMA_G1_CHAN6_RX_DESC_BASE      0x168900 
#define SDMA_G1_CHAN6_CURR_RX_DESC_PTR  0x168910
#define SDMA_G1_CHAN6_TX_DESC_BASE      0x16C900 
#define SDMA_G1_CHAN6_CURR_TX_DESC_PTR  0x16C910
#define SDMA_G1_CHAN6_1ST_TX_DESC_PTR   0x16C914
#define SDMA_G1_CHAN7_CONFIG_REG        0x170900
#define SDMA_G1_CHAN7_COMM_REG          0x170908
#define SDMA_G1_CHAN7_RX_DESC_BASE      0x178900 
#define SDMA_G1_CHAN7_CURR_RX_DESC_PTR  0x178910
#define SDMA_G1_CHAN7_TX_DESC_BASE      0x17C900 
#define SDMA_G1_CHAN7_CURR_TX_DESC_PTR  0x17C910
#define SDMA_G1_CHAN7_1ST_TX_DESC_PTR   0x17C914
/*  MPSCs  */
#define MPSC0_MAIN_CONFIG_LOW   0x000A00 
#define MPSC0_MAIN_CONFIG_HIGH  0x000A04 
#define MPSC0_PROTOCOL_CONFIG   0x000A08 
#define MPSC_CHAN0_REG1         0x000A0C
#define MPSC_CHAN0_REG2         0x000A10
#define MPSC_CHAN0_REG3         0x000A14
#define MPSC_CHAN0_REG4         0x000A18
#define MPSC_CHAN0_REG5         0x000A1C
#define MPSC_CHAN0_REG6         0x000A20 
#define MPSC_CHAN0_REG7         0x000A24
#define MPSC_CHAN0_REG8         0x000A28
#define MPSC_CHAN0_REG9         0x000A2C
#define MPSC_CHAN0_REG10        0x000A30
#define MPSC_CHAN0_REG11        0x000A34
#define MPSC1_MAIN_CONFIG_LOW   0x008A00 
#define MPSC1_MAIN_CONFIG_HIGH  0x008A04 
#define MPSC1_PROTOCOL_CONFIG   0x008A08 
#define MPSC_CHAN1_REG1         0x008A0C
#define MPSC_CHAN1_REG2         0x008A10
#define MPSC_CHAN1_REG3         0x008A14
#define MPSC_CHAN1_REG4         0x008A18
#define MPSC_CHAN1_REG5         0x008A1C
#define MPSC_CHAN1_REG6         0x008A20
#define MPSC_CHAN1_REG7         0x008A24
#define MPSC_CHAN1_REG8         0x008A28
#define MPSC_CHAN1_REG9         0x008A2C
#define MPSC_CHAN1_REG10        0x008A30
#define MPSC_CHAN1_REG11        0x008A34
#define MPSC2_MAIN_CONFIG_LOW   0x010A00 
#define MPSC2_MAIN_CONFIG_HIGH  0x010A04 
#define MPSC2_PROTOCOL_CONFIG   0x010A08 
#define MPSC_CHAN2_REG1         0x010A0C
#define MPSC_CHAN2_REG2         0x010A10
#define MPSC_CHAN2_REG3         0x010A14
#define MPSC_CHAN2_REG4         0x010A18
#define MPSC_CHAN2_REG5         0x010A1C
#define MPSC_CHAN2_REG6         0x010A20 
#define MPSC_CHAN2_REG7         0x010A24
#define MPSC_CHAN2_REG8         0x010A28
#define MPSC_CHAN2_REG9         0x010A2C
#define MPSC_CHAN2_REG10        0x010A30
#define MPSC_CHAN2_REG11        0x010A34
#define MPSC3_MAIN_CONFIG_LOW   0x018A00 
#define MPSC3_MAIN_CONFIG_HIGH  0x018A04
#define MPSC3_PROTOCOL_CONFIG   0x018A08 
#define MPSC_CHAN3_REG1         0x018A0C
#define MPSC_CHAN3_REG2         0x018A10
#define MPSC_CHAN3_REG3         0x018A14
#define MPSC_CHAN3_REG4         0x018A18
#define MPSC_CHAN3_REG5         0x018A1C
#define MPSC_CHAN3_REG6         0x018A20
#define MPSC_CHAN3_REG7         0x018A24
#define MPSC_CHAN3_REG8         0x018A28
#define MPSC_CHAN3_REG9         0x018A2C
#define MPSC_CHAN3_REG10        0x018A30
#define MPSC_CHAN3_REG11        0x018A34
#define MPSC4_MAIN_CONFIG_LOW   0x020A00 
#define MPSC4_MAIN_CONFIG_HIGH  0x020A04
#define MPSC4_PROTOCOL_CONFIG   0x020A08 
#define MPSC_CHAN4_REG1         0x020A0C
#define MPSC_CHAN4_REG2         0x020A10
#define MPSC_CHAN4_REG3         0x020A14
#define MPSC_CHAN4_REG4         0x020A18
#define MPSC_CHAN4_REG5         0x020A1C
#define MPSC_CHAN4_REG6         0x020A20 
#define MPSC_CHAN4_REG7         0x020A24 
#define MPSC_CHAN4_REG8         0x020A28 
#define MPSC_CHAN4_REG9         0x020A2C 
#define MPSC_CHAN4_REG10        0x020A30
#define MPSC_CHAN4_REG11        0x020A34
#define MPSC5_MAIN_CONFIG_LOW   0x028A00 
#define MPSC5_MAIN_CONFIG_HIGH  0x028A04
#define MPSC5_PROTOCOL_CONFIG   0x028A08 
#define MPSC_CHAN5_REG1         0x028A0C
#define MPSC_CHAN5_REG2         0x028A10
#define MPSC_CHAN5_REG3         0x028A14
#define MPSC_CHAN5_REG4         0x028A18
#define MPSC_CHAN5_REG5         0x028A1C
#define MPSC_CHAN5_REG6         0x028A20
#define MPSC_CHAN5_REG7         0x028A24
#define MPSC_CHAN5_REG8         0x028A28
#define MPSC_CHAN5_REG9         0x028A2C
#define MPSC_CHAN5_REG10        0x028A30
#define MPSC_CHAN5_REG11        0x028A34
#define MPSC6_MAIN_CONFIG_LOW   0x030A00 
#define MPSC6_MAIN_CONFIG_HIGH  0x030A04
#define MPSC6_PROTOCOL_CONFIG   0x030A08 
#define MPSC_CHAN6_REG1         0x030A0C
#define MPSC_CHAN6_REG2         0x030A10
#define MPSC_CHAN6_REG3         0x030A14
#define MPSC_CHAN6_REG4         0x030A18
#define MPSC_CHAN6_REG5         0x030A1C
#define MPSC_CHAN6_REG6         0x030A20
#define MPSC_CHAN6_REG7         0x030A24
#define MPSC_CHAN6_REG8         0x030A28
#define MPSC_CHAN6_REG9         0x030A2C
#define MPSC_CHAN6_REG10        0x030A30
#define MPSC_CHAN6_REG11        0x030A34
#define MPSC7_MAIN_CONFIG_LOW   0x038A00 
#define MPSC7_MAIN_CONFIG_HIGH  0x038A04
#define MPSC7_PROTOCOL_CONFIG   0x038A08 
#define MPSC_CHAN7_REG1         0x038A0C
#define MPSC_CHAN7_REG2         0x038A10
#define MPSC_CHAN7_REG3         0x038A14
#define MPSC_CHAN7_REG4         0x038A18
#define MPSC_CHAN7_REG5         0x038A1C
#define MPSC_CHAN7_REG6         0x038A20
#define MPSC_CHAN7_REG7         0x038A24
#define MPSC_CHAN7_REG8         0x038A28
#define MPSC_CHAN7_REG9         0x038A2C
#define MPSC_CHAN7_REG10        0x038A30
#define MPSC_CHAN7_REG11        0x038A34
/*  FlexTDMs  */
#define FXTDM0_TDPR0_BLK0_BASE  0x000B00    /* TDPR0 - Transmit Dual Port RAM. block size 0xff */
#define FXTDM0_TDPR0_BLK1_BASE  0x001B00 
#define FXTDM0_TDPR0_BLK2_BASE  0x002B00 
#define FXTDM0_TDPR0_BLK3_BASE  0x003B00 
#define FXTDM0_RDPR0_BLK0_BASE  0x004B00    /* RDPR0 - Receive Dual Port RAM. block size 0xff */
#define FXTDM0_RDPR0_BLK1_BASE  0x005B00 
#define FXTDM0_RDPR0_BLK2_BASE  0x006B00 
#define FXTDM0_RDPR0_BLK3_BASE  0x007B00 
#define FXTDM0_TX_READ_PTR      0x008B00
#define FXTDM0_RX_READ_PTR      0x008B04
#define FXTDM0_CONFIG_REG       0x008B08
#define FXTDM0_AUX_CHANA_TX_REG 0x008B0C
#define FXTDM0_AUX_CHANA_RX_REG 0x008B10
#define FXTDM0_AUX_CHANB_TX_REG 0x008B14
#define FXTDM0_AUX_CHANB_RX_REG 0x008B18
#define FXTDM1_TDPR1_BLK0_BASE  0x010B00 
#define FXTDM1_TDPR1_BLK1_BASE  0x011B00 
#define FXTDM1_TDPR1_BLK2_BASE  0x012B00 
#define FXTDM1_TDPR1_BLK3_BASE  0x013B00 
#define FXTDM1_RDPR1_BLK0_BASE  0x014B00 
#define FXTDM1_RDPR1_BLK1_BASE  0x015B00 
#define FXTDM1_RDPR1_BLK2_BASE  0x016B00 
#define FXTDM1_RDPR1_BLK3_BASE  0x017B00 
#define FXTDM1_TX_READ_PTR      0x018B00
#define FXTDM1_RX_READ_PTR      0x018B04
#define FXTDM1_CONFIG_REG       0x018B08
#define FXTDM1_AUX_CHANA_TX_REG 0x018B0C
#define FXTDM1_AUX CHANA_RX_REG 0x018B10
#define FLTDM1_AUX_CHANB_TX_REG 0x018B14
#define FLTDM1_AUX_CHANB_RX_REG 0x018B18
#define FLTDM2_TDPR2_BLK0_BASE  0x020B00
#define FLTDM2_TDPR2_BLK1_BASE  0x021B00 
#define FLTDM2_TDPR2_BLK2_BASE  0x022B00
#define FLTDM2_TDPR2_BLK3_BASE  0x023B00
#define FLTDM2_RDPR2_BLK0_BASE  0x024B00
#define FLTDM2_RDPR2_BLK1_BASE  0x025B00
#define FLTDM2_RDPR2_BLK2_BASE  0x026B00
#define FLTDM2_RDPR2_BLK3_BASE  0x027B00
#define FLTDM2_TX_READ_PTR      0x028B00
#define FLTDM2_RX_READ_PTR      0x028B04
#define FLTDM2_CONFIG_REG       0x028B08
#define FLTDM2_AUX_CHANA_TX_REG 0x028B0C
#define FLTDM2_AUX_CHANA_RX_REG 0x028B10
#define FLTDM2_AUX_CHANB_TX_REG 0x028B14
#define FLTDM2_AUX_CHANB_RX_REG 0x028B18
#define FLTDM3_TDPR3_BLK0_BASE  0x030B00
#define FLTDM3_TDPR3_BLK1_BASE  0x031B00
#define FLTDM3_TDPR3_BLK2_BASE  0x032B00
#define FLTDM3_TDPR3_BLK3_BASE  0x033B00
#define FXTDM3_RDPR3_BLK0_BASE  0x034B00
#define FXTDM3_RDPR3_BLK1_BASE  0x035B00
#define FXTDM3_RDPR3_BLK2_BASE  0x036B00
#define FXTDM3_RDPR3_BLK3_BASE  0x037B00
#define FXTDM3_TX_READ_PTR      0x038B00
#define FXTDM3_RX_READ_PTR      0x038B04
#define FXTDM3_CONFIG_REG       0x038B08
#define FXTDM3_AUX_CHANA_TX_REG 0x038B0C
#define FXTDM3_AUX_CHANA_RX_REG 0x038B10
#define FXTDM3_AUX_CHANB_TX_REG 0x038B14
#define FXTDM3_AUX_CHANB_RX_REG 0x038B18
/*  Baud Rate Generators  */
#define BRG0_CONFIG_REG     0x102A00 
#define BRG0_BAUD_TUNE_REG  0x102A04 
#define BRG1_CONFIG_REG     0x102A08 
#define BRG1_BAUD_TUNE_REG  0x102A0C 
#define BRG2_CONFIG_REG     0x102A10 
#define BRG2_BAUD_TUNE_REG  0x102A14 
#define BRG3_CONFIG_REG     0x102A18 
#define BRG3_BAUD_TUNE_REG  0x102A1C 
#define BRG4_CONFIG_REG     0x102A20 
#define BRG4_BAUD_TUNE_REG  0x102A24 
#define BRG5_CONFIG_REG     0x102A28 
#define BRG5_BAUD_TUNE_REG  0x102A2C 
#define BRG6_CONFIG_REG     0x102A30 
#define BRG6_BAUD_TUNE_REG  0x102A34 
#define BRG7_CONFIG_REG     0x102A38 
#define BRG7_BAUD_TUNE_REG  0x102A3C 
/*  Routing Registers  */
#define ROUTE_MAIN_REG      0x101A00 
#define ROUTE_RX_CLOCK_REG  0x101A10 
#define ROUTE_TX_CLOCK_REG  0x101A20 
#define PORT_ROUTING_REGISTER 0x101a30
/*  General Purpose Ports  */
#define GPP_CONFIG0     0x100A00 
#define GPP_CONFIG1     0x100A04 
#define GPP_CONFIG2     0x100A08 
#define GPP_CONFIG3     0x100A0C 
#define GPP_IO0         0x100A20 
#define GPP_IO1         0x100A24 
#define GPP_IO2         0x100A28 
#define GPP_IO3         0x100A2C 
#define GPP_DATA0       0x100A40 
#define GPP_DATA1       0x100A44 
#define GPP_DATA2       0x100A48 
#define GPP_DATA3       0x100A4C 
#define GPP_LEVEL0      0x100A60 
#define GPP_LEVEL1      0x100A64 
#define GPP_LEVEL2      0x100A68 
#define GPP_LEVEL3      0x100A6C 
/*  Watchdog  */
#define WD_CONFIG_REG   0x101A80 
#define WD_VALUE_REG    0x101A84 

/* Communication Unit Arbiter  */
#define COMM_UNIT_ARBTR_CONFIG_REG 0x101AC0
#define COMM_UNIT_ARBTR_EXT_REG    0x101AC4

/* mcsc registers */


/* MCDMA registers */
#define MCDMA_GLOBAL_CONTROL_REGISTER   0x044a00

#define MCSC_GLOBAL_INTERRUPT_CAUSE     0x048a04
#define MCSC_EXTENDED_INTERRUPT_CAUSE   0x048a08

#define MCSC_GLOBAL_INTERRUPT_MASK      0x048a0c
#define MCSC_EXTENDED_INTERRUPT_MASK    0x048a10

#define IQC_FIRST                       0x048a14
#define IQC_LAST                        0x048a18
#define IQC_HEAD                        0x048a1c
#define IQC_TAIL                        0x048a20

#define IQC_ENABLE_INTERRUPTS_REGISTER  0x048a24

/* MCSC registers */
#define MCSC_GLOBAL_CONTROL_REGISTER    0x48a00
         
#endif /* __INCgt96132Rh */