gt96132reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/****************************************/
/* Ethernet, MPSC and GPP port		*/
/****************************************/

#define MAIN_ROUTING_REGISTER			0x101A00
#define RECEIVE_CLOCK_ROUTING_REGISTER		0x101A10
#define TRANSMIT_CLOCK_ROUTING_REGISTER		0x101A20
#define SERIAL_CAUSE_REGISTER			0x103a00
#define SERINT0_MASK_REGISTER			0x103a80
#define SERINT1_MASK_REGISTER			0x103a88
#define ETHERNET0_CAUSE_REGISTER		0x084850
#define ETHERNET0_MASK_REGISTER			0x084858
#define ETHERNET1_CAUSE_REGISTER		0x088850
#define ETHERNET1_MASK_REGISTER			0x088858
#define SDMA_CAUSE_REGISTER			0x103A10
#define SDMA_MASK_REGISTER			0x103A90
#define MPSC0_CAUSE_REGISTER			0x103a20
#define MPSC0_MASK_REGISTER			0x103aa0
#define MPSC1_CAUSE_REGISTER			0x103a24
#define MPSC1_MASK_REGISTER			0x103aa4
#define MPSC2_CAUSE_REGISTER			0x103a28
#define MPSC2_MASK_REGISTER			0x103aa8
#define MPSC3_CAUSE_REGISTER			0x103a2c
#define MPSC3_MASK_REGISTER			0x103aac
#define MPSC4_CAUSE_REGISTER			0x103a30
#define MPSC4_MASK_REGISTER			0x103ab0
#define MPSC5_CAUSE_REGISTER			0x103a34
#define MPSC5_MASK_REGISTER			0x103ab4
#define MPSC6_CAUSE_REGISTER			0x103a38
#define MPSC6_MASK_REGISTER			0x103ab8
#define MPSC7_CAUSE_REGISTER			0x103a3c
#define MPSC7_MASK_REGISTER			0x103abc
#define FLEX_TDM_CAUSE_REGISTER			0x103a40
#define FLEX_TDM_MASK_REGISTER			0x103ac0
#define BRG_CAUSE_REGISTER			0x103a48
#define BRG_MASK_REGISTER			0x103ac8
#define GPP0_CAUSE_REGISTER			0x103a50
#define GPP0_MASK_REGISTER			0x103ad0
#define GPP1_CAUSE_REGISTER			0x103a54
#define GPP1_MASK_REGISTER			0x103ad4
#define GPP2_CAUSE_REGISTER			0x103a58
#define GPP2_MASK_REGISTER			0x103ad8
#define GPP3_CAUSE_REGISTER			0x103a5c
#define GPP3_MASK_REGISTER			0x103adc

/****************************************/
/* PCI Configuration   			*/
/****************************************/

#define PCI_DEVICE_AND_VENDOR_ID 		0x000
#define PCI_STATUS_AND_COMMAND			0x004
#define PCI_CLASS_CODE_AND_REVISION_ID 		0x008
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	0x00C
#define PCI_SCS_1_0_BASE_ADDRESS	 	0x010
#define PCI_SCS_3_2_BASE_ADDRESS 		0x014
#define PCI_1SCS_1_0_BASE_ADDRESS	 	0x090
#define PCI_1SCS_3_2_BASE_ADDRESS 		0x094
#define PCI_CS_2_0_BASE_ADDRESS 		0x018
#define PCI_CS_3_BOOTCS_BASE_ADDRESS		0x01C
#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
/* Erez */
#define PCI_0INTERNAL_REGISTERS_SPACE_SIZE	0xC20
#define PCI_1INTERNAL_REGISTERS_SPACE_SIZE	0xCA0
/* Erez End */
#define PCI_0SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	0x02C
#define EXPANSION_ROM_BASE_ADDRESS_REGISTER	0x030
#define PCI_INTERRUPT_PIN_AND_LINE		0x03C

/****************************************/
/* PCI Control                          */
/****************************************/

#define PCI_0ARBITER_CONTROL			0x101ae0
#define PCI_1ARBITER_CONTROL			0x101ae4

/****************************************/
/* PCI Configuration, Function 1	*/
/****************************************/

#define PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS 	0x110
#define PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS 	0x114
#define PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS	0x11C
#define PCI_1SWAPPED_SCS_1_0_BASE_ADDRESS 	0x190
#define PCI_1SWAPPED_SCS_3_2_BASE_ADDRESS 	0x194
#define PCI_1SWAPPED_CS_3_BOOTCS_BASE_ADDRESS	0x19c


/****************************************/
/* I20 Support registers		*/
/****************************************/

#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE	0x010
#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE  	0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 	0x018
#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE  	0x01C
#define INBOUND_DOORBELL_REGISTER_PCI_SIDE  	0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 	0x02C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
#define QUEUE_CONTROL_REGISTER_PCI_SIDE 	0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 	0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C

#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE	0X1C10
#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE  	0X1C14
#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 	0X1C18
#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE  	0X1C1C
#define INBOUND_DOORBELL_REGISTER_CPU_SIDE  	0X1C20
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0X1C24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0X1C28
#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 	0X1C2C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0X1C30
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE  0X1C34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0X1C40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0X1C44
#define QUEUE_CONTROL_REGISTER_CPU_SIDE 	0X1C50
#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 	0X1C54
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C60
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C64
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C68
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C6C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C70
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C74
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0X1C78
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0X1C7C


/* Ethernet Ports */
#define ETH_PHY_ADDR_REG	 		0x080800 
#define ETH_SMI_REG				0x080810 
#define GT_SMIR_REG				ETH_SMI_REG
#define	ETHERNET_PORTS_DIFFERENCE_OFFSETS	0x4000

#define ETH0_PORT_CONFIG_REG			0x084800 
#define ETH0_PORT_CONFIG_EXT_REG		0x084808 
#define ETH0_PORT_COMMAND_REG			0x084810 
#define ETH0_PORT_STATUS_REG			0x084818 
#define ETH0_SERIAL_PARAMETRS_REG		0x084820 
#define ETH0_HASH_TABLE_PTR_REG			0x084828 
#define ETH0_FLOW_CNTROL_SOURCE_ADDR_LO    0x084830 
#define ETH0_FLOW_CNTROL_SOURCE_ADDR_HO    0x084838 
#define ETH0_SDMA_CONFIG_REG          0x084840 
#define ETH0_SDMA_COMMAND_REG            0x084848 
#define ETH0_INTERRUPT_CAUSE_REG            0x084850 
#define ETH0_INTERRUPT_MASK_REG             0x084858

#define ETHER0_TOS_PRIORITY_0_LOW       0x084860
#define ETHER0_TOS_PRIORITY_0_HIGH      0x084864
#define ETHER0_TOS_PRIORITY_1_LOW       0x084868
#define ETHER0_TOS_PRIORITY_1_HIGH      0x08486c
#define ETHER0_VLAN_TO_PRIORITY         0x084870
 
#define ETH0_FIRST_RX_DESC_PTR0         0x084880
#define ETH0_FIRST_RX_DESC_PTR1         0x084884
#define ETH0_FIRST_RX_DESC_PTR2         0x084888
#define ETH0_FIRST_RX_DESC_PTR3         0x08488C
#define ETH0_CURRENT_RX_DESC_PTR0        0x0848A0
#define ETH0_CURRENT_RX_DESC_PTR1        0x0848A4
#define ETH0_CURRENT_RX_DESC_PTR2        0x0848A8
#define ETH0_CURRENT_RX_DESC_PTR3        0x0848AC
#define ETH0_CURRENT_TX_DESC_PTR0        0x0848E0
#define ETH0_CURRENT_TX_DESC_PTR1        0x0848E4
#define ETH0_MIB_COUNTER_BASE           0x085800 

#define ETHER1_PORT_CONFIG_REG          0x088800 
#define ETHER1_PORT_CONFIG_EXT_REG      0x088808 
#define ETHER1_PORT_COMM_REG            0x088810 
#define ETHER1_PORT_STATUS_REG          0x088818 
#define ETHER1_SER_PARAM_REG            0x088820 
#define ETHER1_HASH_TBL_PTR_REG         0x088828 
#define ETHER1_FLOW_CNTRL_SRC_ADDR_L    0x088830 
#define ETHER1_FLOW_CNTRL_SRC_ADDR_H    0x088838 
#define ETHER1_SDMA_CONFIG_REG          0x088840 
#define ETHER1_SDMA_COMM_REG            0x088848 
#define ETHER1_INT_CAUSE_REG            0x088850 
#define ETHER1_INT_MASK_REG             0x088858 
#define ETHER1_1ST_RX_DESC_PTR0         0x088880
#define ETHER1_1ST_RX_DESC_PTR1         0x088884
#define ETHER1_1ST_RX_DESC_PTR2         0x088888
#define ETHER1_1ST_RX_DESC_PTR3         0x08888C
#define ETHER1_CURR_RX_DESC_PTR0        0x0888A0
#define ETHER1_CURR_RX_DESC_PTR1        0x0888A4
#define ETHER1_CURR_RX_DESC_PTR2        0x0888A8
#define ETHER1_CURR_RX_DESC_PTR3        0x0888AC
#define ETHER1_CURR_TX_DESC_PTR0        0x0888E0
#define ETHER1_CURR_TX_DESC_PTR1        0x0888E4
#define ETHER1_MIB_COUNT_BASE           0x089800 

/* SDMAs */
#define SDMA_GROUP_CONFIG_REG   0x101AF0
/* SDMA Group 0 */
#define SDMA_G0_CHAN0_CONFIG_REG        0x000900 
#define SDMA_G0_CHAN0_COMM_REG          0x000908 
#define SDMA_G0_CHAN0_RX_DESC_BASE      0x008900 
#define SDMA_G0_CHAN0_CURR_RX_DESC_PTR  0x008910
#define SDMA_G0_CHAN0_TX_DESC_BASE      0x00C900 
#define SDMA_G0_CHAN0_CURR_TX_DESC_PTR  0x00C910
#define SDMA_G0_CHAN0_1ST_TX_DESC_PTR   0x00C914
#define SDMA_G0_CHAN1_CONFIG_REG        0x010900
#define SDMA_G0_CHAN1_COMM_REG          0x010908
#define SDMA_G0_CHAN1_RX_DESC_BASE      0x018900 
#define SDMA_G0_CHAN1_CURR_RX_DESC_PTR  0x018910
#define SDMA_G0_CHAN1_TX_DESC_BASE      0x01C900 
#define SDMA_G0_CHAN1_CURR_TX_DESC_PTR  0x01C910
#define SDMA_G0_CHAN1_1ST_TX_DESC_PTR   0x01C914
#define SDMA_G0_CHAN2_CONFIG_REG        0x020900
#define SDMA_G0_CHAN2_COMM_REG          0x020908
#define SDMA_G0_CHAN2_RX_DESC_BASE      0x028900 
#define SDMA_G0_CHAN2_CURR_RX_DESC_PTR  0x028910
#define SDMA_G0_CHAN2_TX_DESC_BASE      0x02C900 
#define SDMA_G0_CHAN2_CURR_TX_DESC_PTR  0x02C910
#define SDMA_G0_CHAN2_1ST_TX_DESC_PTR   0x02C914
#define SDMA_G0_CHAN3_CONFIG_REG        0x030900
#define SDMA_G0_CHAN3_COMM_REG          0x030908
#define SDMA_G0_CHAN3_RX_DESC_BASE      0x038900 
#define SDMA_G0_CHAN3_CURR_RX_DESC_PTR  0x038910
#define SDMA_G0_CHAN3_TX_DESC_BASE      0x03C900 
#define SDMA_G0_CHAN3_CURR_TX_DESC_PTR  0x03C910
#define SDMA_G0_CHAN3_1ST_TX_DESC_PTR   0x03C914
#define SDMA_G0_CHAN4_CONFIG_REG        0x040900
#define SDMA_G0_CHAN4_COMM_REG          0x040908
#define SDMA_G0_CHAN4_RX_DESC_BASE      0x048900 
#define SDMA_G0_CHAN4_CURR_RX_DESC_PTR  0x048910
#define SDMA_G0_CHAN4_TX_DESC_BASE      0x04C900 
#define SDMA_G0_CHAN4_CURR_TX_DESC_PTR  0x04C910
#define SDMA_G0_CHAN4_1ST_TX_DESC_PTR   0x04C914
#define SDMA_G0_CHAN5_CONFIG_REG        0x050900
#define SDMA_G0_CHAN5_COMM_REG          0x050908
#define SDMA_G0_CHAN5_RX_DESC_BASE      0x058900 
#define SDMA_G0_CHAN5_CURR_RX_DESC_PTR  0x058910
#define SDMA_G0_CHAN5_TX_DESC_BASE      0x05C900 
#define SDMA_G0_CHAN5_CURR_TX_DESC_PTR  0x05C910
#define SDMA_G0_CHAN5_1ST_TX_DESC_PTR   0x05C914
#define SDMA_G0_CHAN6_CONFIG_REG        0x060900
#define SDMA_G0_CHAN6_COMM_REG          0x060908
#define SDMA_G0_CHAN6_RX_DESC_BASE      0x068900 
#define SDMA_G0_CHAN6_CURR_RX_DESC_PTR  0x068910
#define SDMA_G0_CHAN6_TX_DESC_BASE      0x06C900 
#define SDMA_G0_CHAN6_CURR_TX_DESC_PTR  0x06C910
#define SDMA_G0_CHAN6_1ST_TX_DESC_PTR   0x06C914
#define SDMA_G0_CHAN7_CONFIG_REG        0x070900
#define SDMA_G0_CHAN7_COMM_REG          0x070908
#define SDMA_G0_CHAN7_RX_DESC_BASE      0x078900
#define SDMA_G0_CHAN7_CURR_RX_DESC_PTR  0x078910
#define SDMA_G0_CHAN7_TX_DESC_BASE      0x07C900 
#define SDMA_G0_CHAN7_CURR_TX_DESC_PTR  0x07C910
#define SDMA_G0_CHAN7_1ST_TX_DESC_PTR   0x07C914
/* SDMA Group 1 */
#define SDMA_G1_CHAN0_CONFIG_REG        0x100900
#define SDMA_G1_CHAN0_COMM_REG          0x100908
#define SDMA_G1_CHAN0_RX_DESC_BASE      0x108900 
#define SDMA_G1_CHAN0_CURR_RX_DESC_PTR  0x108910
#define SDMA_G1_CHAN0_TX_DESC_BASE      0x10C900 
#define SDMA_G1_CHAN0_CURR_TX_DESC_PTR  0x10C910 
#define SDMA_G1_CHAN0_1ST_TX_DESC_PTR   0x10C914
#define SDMA_G1_CHAN1_CONFIG_REG        0x110900
#define SDMA_G1_CHAN1_COMM_REG          0x110908
#define SDMA_G1_CHAN1_RX_DESC_BASE      0x118900 
#define SDMA_G1_CHAN1_CURR_RX_DESC_PTR  0x118910
#define SDMA_G1_CHAN1_TX_DESC_BASE      0x11C900 
#define SDMA_G1_CHAN1_CURR_TX_DESC_PTR  0x11C910
#define SDMA_G1_CHAN1_1ST_TX_DESC_PTR   0x11C914
#define SDMA_G1_CHAN2_CONFIG_REG        0x120900
#define SDMA_G1_CHAN2_COMM_REG          0x120908
#define SDMA_G1_CHAN2_RX_DESC_BASE      0x128900 
#define SDMA_G1_CHAN2_CURR_RX_DESC_PTR  0x128910
#define SDMA_G1_CHAN2_TX_DESC_BASE      0x12C900 
#define SDMA_G1_CHAN2_CURR_TX_DESC_PTR  0x12C910
#define SDMA_G1_CHAN2_1ST_TX_DESC_PTR   0x12C914