gt96132reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: gt96132reg.h,v 1.2 2002/02/13 11:18:19 pefo Exp $ */

/*
 * Copyright (c) 2001-2002 Galileo Technology
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Galileo Technology
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */
/* GT96132R.h - GT96132 Internal registers definition file */

/* Copyright - Galileo technology. */

#ifndef __INCgt96132Rh 
#define __INCgt96132Rh

#ifndef GT96132
#define GT96132
#endif

#include <machine/asm.h>

#define HTOLE32(v)      ((((v) & 0xff) << 24) | (((v) & 0xff00) << 8) | \
                         (((v) >> 24) & 0xff) | (((v) >> 8) & 0xff00))

#define GT_WRITE(ofs, data) \
    *(volatile u_int32_t *)(GT_BASE_ADDR+ofs) = HTOLE32(data)
#define GT_WRITE_NOSWAP(ofs, data) \
    *(volatile u_int32_t *)(GT_BASE_ADDR+ofs) = (data)

#define GT_READ(ofs) \
    HTOLE32(*(volatile u_int32_t *)(GT_BASE_ADDR+ofs))
#define GT_READ_NOSWAP(ofs) \
    (*(volatile u_int32_t *)(GT_BASE_ADDR+ofs))

#if defined(GT_HIGH)
#define GT_BASE_ADDR                    0xfe000000
#else
#define GT_BASE_ADDR                    0x14000000
#endif
#define GT_BASE_ADDR_DEFAULT            0x14000000

/****************************************/
/* CPU Configuration 			*/
/****************************************/

#define CPU_INTERFACE_CONFIGURATION		0x000
#define	CPU_CONF				CPU_INTERFACE_CONFIGURATION
#define	MULTI_GT_REGISTER			0x120

/****************************************/
/* Processor Address Space		*/
/****************************************/

#define SCS_1_0_LOW_DECODE_ADDRESS		0x008
#define SCS_1_0_HIGH_DECODE_ADDRESS		0x010
#define SCS_3_2_LOW_DECODE_ADDRESS		0x018
#define SCS_3_2_HIGH_DECODE_ADDRESS		0x020
#define CS_2_0_LOW_DECODE_ADDRESS		0x028
#define CS_2_0_HIGH_DECODE_ADDRESS		0x030
#define CS_3_BOOTCS_LOW_DECODE_ADDRESS		0x038
#define CS_3_BOOTCS_HIGH_DECODE_ADDRESS		0x040
#define PCI_0I_O_LOW_DECODE_ADDRESS		0x048
#define PCI_0I_O_HIGH_DECODE_ADDRESS		0x050
#define PCI_0MEMORY0_LOW_DECODE_ADDRESS		0x058
#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS	0x060
#define PCI_0MEMORY1_LOW_DECODE_ADDRESS		0x080
#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS	0x088
#define PCI_1I_O_LOW_DECODE_ADDRESS		0x090
#define PCI_1I_O_HIGH_DECODE_ADDRESS		0x098
#define PCI_1MEMORY0_LOW_DECODE_ADDRESS		0x0a0
#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS	0x0a8
#define PCI_1MEMORY1_LOW_DECODE_ADDRESS		0x0b0
#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS	0x0b8
#define INTERNAL_SPACE_DECODE			0x068
#define CPU_BUS_ERROR_LOW_ADDRESS 		0x070
#define CPU_BUS_ERROR_HIGH_ADDRESS 		0x078
#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER	0x0c0
#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER	0x0c8
#define SCS_1_0_ADDRESS_REMAP			0x0d0
#define SCS_3_2_ADDRESS_REMAP			0x0d8
#define CS_2_0_ADDRESS_REMAP			0x0e0
#define CS_3_BOOTCS_ADDRESS_REMAP		0x0e8
#define PCI_0I_O_ADDRESS_REMAP			0x0f0
#define PCI_0MEMORY0_ADDRESS_REMAP		0x0f8
#define PCI_0MEMORY1_ADDRESS_REMAP		0x100
#define PCI_1I_O_ADDRESS_REMAP			0x108
#define PCI_1MEMORY0_ADDRESS_REMAP		0x110
#define PCI_1MEMORY1_ADDRESS_REMAP		0x118

/****************************************/
/* SDRAM and Device Address Space	*/
/****************************************/
	
#define SCS_0_LOW_DECODE_ADDRESS		0x400
#define SCS_0_HIGH_DECODE_ADDRESS		0x404
#define SCS_1_LOW_DECODE_ADDRESS		0x408
#define SCS_1_HIGH_DECODE_ADDRESS		0x40C
#define SCS_2_LOW_DECODE_ADDRESS		0x410
#define SCS_2_HIGH_DECODE_ADDRESS		0x414
#define SCS_3_LOW_DECODE_ADDRESS		0x418
#define SCS_3_HIGH_DECODE_ADDRESS		0x41C
#define CS_0_LOW_DECODE_ADDRESS			0x420
#define CS_0_HIGH_DECODE_ADDRESS		0x424
#define CS_1_LOW_DECODE_ADDRESS			0x428
#define CS_1_HIGH_DECODE_ADDRESS		0x42C
#define CS_2_LOW_DECODE_ADDRESS			0x430
#define CS_2_HIGH_DECODE_ADDRESS		0x434
#define CS_3_LOW_DECODE_ADDRESS			0x438
#define CS_3_HIGH_DECODE_ADDRESS		0x43C
#define BOOTCS_LOW_DECODE_ADDRESS		0x440
#define BOOTCS_HIGH_DECODE_ADDRESS		0x444
#define ADDRESS_DECODE_ERROR			0x470
#define ADDRESS_DECODE				0x47C

/****************************************/
/* SDRAM Configuration			*/
/****************************************/

#define SDRAM_CONFIGURATION	 		0x448
#define SDRAM_OPERATION_MODE			0x474
#define SDRAM_ADDRESS_DECODE			0x47C

/****************************************/
/* SDRAM Parameters			*/
/****************************************/
			
#define SDRAM_BANK0PARAMETERS			0x44C
#define SDRAM_BANK1PARAMETERS			0x450
#define SDRAM_BANK2PARAMETERS			0x454
#define SDRAM_BANK3PARAMETERS			0x458

/****************************************/
/* Device Parameters			*/
/****************************************/

#define DEVICE_BANK0PARAMETERS			0x45C
#define DEVICE_BANK1PARAMETERS			0x460
#define DEVICE_BANK2PARAMETERS			0x464
#define DEVICE_BANK3PARAMETERS			0x468
#define DEVICE_BOOT_BANK_PARAMETERS		0x46C

#define	GT_DEV0_PAR				DEVICE_BANK0PARAMETERS
#define	GT_DEV1_PAR				DEVICE_BANK1PARAMETERS
#define	GT_DEV2_PAR				DEVICE_BANK2PARAMETERS
#define	GT_DEV3_PAR				DEVICE_BANK3PARAMETERS
#define	GT_BOOT_PAR				DEVICE_BOOT_BANK_PARAMETERS

/****************************************/
/* DMA Record				*/
/****************************************/

#define CHANNEL0_DMA_BYTE_COUNT			0x800
#define CHANNEL1_DMA_BYTE_COUNT	 		0x804
#define CHANNEL2_DMA_BYTE_COUNT	 		0x808
#define CHANNEL3_DMA_BYTE_COUNT	 		0x80C
#define CHANNEL0_DMA_SOURCE_ADDRESS		0x810
#define CHANNEL1_DMA_SOURCE_ADDRESS		0x814
#define CHANNEL2_DMA_SOURCE_ADDRESS		0x818
#define CHANNEL3_DMA_SOURCE_ADDRESS		0x81C
#define CHANNEL0_DMA_DESTINATION_ADDRESS	0x820
#define CHANNEL1_DMA_DESTINATION_ADDRESS	0x824
#define CHANNEL2_DMA_DESTINATION_ADDRESS	0x828
#define CHANNEL3_DMA_DESTINATION_ADDRESS	0x82C
#define CHANNEL0NEXT_RECORD_POINTER		0x830
#define CHANNEL1NEXT_RECORD_POINTER		0x834
#define CHANNEL2NEXT_RECORD_POINTER		0x838
#define CHANNEL3NEXT_RECORD_POINTER		0x83C
#define CHANNEL0CURRENT_DESCRIPTOR_POINTER	0x870
#define CHANNEL1CURRENT_DESCRIPTOR_POINTER	0x874
#define CHANNEL2CURRENT_DESCRIPTOR_POINTER	0x878
#define CHANNEL3CURRENT_DESCRIPTOR_POINTER	0x87C

/****************************************/
/* DMA Channel Control			*/
/****************************************/

#define CHANNEL0CONTROL				0x840
#define CHANNEL1CONTROL				0x844
#define CHANNEL2CONTROL				0x848
#define CHANNEL3CONTROL				0x84C

/****************************************/
/* DMA Arbiter				*/
/****************************************/

#define ARBITER_CONTROL				0x860

/****************************************/
/* Timer_Counter 			*/
/****************************************/

#define TIMER_COUNTER0				0x850
#define TIMER_COUNTER1				0x854
#define TIMER_COUNTER2				0x858
#define TIMER_COUNTER3				0x85C
#define TIMER_COUNTER_CONTROL			0x864

/****************************************/
/* PCI Internal  			*/
/****************************************/

#define PCI_0COMMAND				0xC00
#define PCI_0TIMEOUT_RETRY			0xC04
#define PCI_0SCS_1_0_BANK_SIZE			0xC08
#define PCI_0SCS_3_2_BANK_SIZE			0xC0C
#define PCI_0CS_2_0_BANK_SIZE			0xC10
#define PCI_0CS_3_BOOTCS_BANK_SIZE		0xC14
#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 	0xC3C
#define PCI_0PREFETCH_MAX_BURST_SIZE		0xc40
#define PCI_0SCS_1_0_BASE_ADDRESS_REMAP		0xC48
#define PCI_0SCS_3_2_BASE_ADDRESS_REMAP		0xC4C
#define PCI_0CS_2_0_BASE_ADDRESS_REMAP		0xC50
#define PCI_0CS_3_BOOTCS_ADDRESS_REMAP		0xC54
#define PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS_REMAP	0xC58
#define PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS_REMAP	0xC5C
#define PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS_REMAP	0xC64
#define PCI_0CONFIGURATION_ADDRESS 		0xCF8
#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER	0xCFC
#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	0xC34
#define PCI_1COMMAND				0xc80
#define PCI_1TIMEOUT_RETRY			0xc84
#define PCI_1SCS_1_0_BANK_SIZE			0xc88
#define PCI_1SCS_3_2_BANK_SIZE			0xc8c
#define PCI_1CS_2_0_BANK_SIZE			0xc90
#define PCI_1CS_3_BOOTCS_BANK_SIZE		0xc94
#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 	0xcbc
#define PCI_1PREFETCH_MAX_BURST_SIZE		0xcc0
#define PCI_1SCS_1_0_BASE_ADDRESS_REMAP		0xcc8
#define PCI_1SCS_3_2_BASE_ADDRESS_REMAP		0xccc
#define PCI_1CS_2_0_BASE_ADDRESS_REMAP		0xcd0
#define PCI_1CS_3_BOOTCS_ADDRESS_REMAP		0xcd4
#define PCI_1SWAPPED_SCS_1_0_BASE_ADDRESS_REMAP	0xcd8
#define PCI_1SWAPPED_SCS_3_2_BASE_ADDRESS_REMAP	0xcdc
#define PCI_1SWAPPED_CS_3_BOOTCS_BASE_ADDRESS_REMAP	0xce4
#define PCI_1CONFIGURATION_ADDRESS 		0xcf0
#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER	0xcf4
#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	0xc30

/****************************************/
/* Interrupts	  			*/
/****************************************/
  
#define INTERRUPT_MAIN_CAUSE_REGISTER		0xc18
#define INTERRUPT0_MAIN_MASK_REGISTER		0xc1c
#define INTERRUPT1_MAIN_MASK_REGISTER		0xc24
#define INTERRUPT_HIGH_CAUSE_REGISTER		0xc98
#define INTERRUPT0_HIGH_MASK_REGISTER		0xc9c
#define INTERRUPT1_HIGH_MASK_REGISTER		0xcA4
#define INTERRUPT0_SELECT_REGISTER		0xc70
#define INTERRUPT1_SELECT_REGISTER		0xc74
#define INTERRUPT_CAUSE_REGISTER		0xC18
#define HIGH_INTERRUPT_CAUSE_REGISTER		0xc98
#define CPU_INTERRUPT_MASK_REGISTER		0xC1C
#define CPU_HIGH_INTERRUPT_MASK_REGISTER	0xc9c
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER	0xC24
#define PCI_0HIGH_INTERRUPT_CAUSE_MASK_REGISTER	0xca4
#define PCI_0SERR0_MASK				0xC28
#define PCI_1SERR0_MASK				0xca8