gt64260reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#define TIMER_COUNTER_4_7_INTERRUPT_MASK      		0x96c

/****************************************/
/* PCI Slave Address Decoding           */
/****************************************/
        
#define PCI_0SCS_0_BANK_SIZE				0xc08
#define PCI_1SCS_0_BANK_SIZE				0xc88
#define PCI_0SCS_1_BANK_SIZE				0xd08
#define PCI_1SCS_1_BANK_SIZE				0xd88
#define PCI_0SCS_2_BANK_SIZE				0xc0c
#define PCI_1SCS_2_BANK_SIZE				0xc8c
#define PCI_0SCS_3_BANK_SIZE				0xd0c
#define PCI_1SCS_3_BANK_SIZE				0xd8c
#define PCI_0CS_0_BANK_SIZE				0xc10
#define PCI_1CS_0_BANK_SIZE				0xc90
#define PCI_0CS_1_BANK_SIZE				0xd10
#define PCI_1CS_1_BANK_SIZE				0xd90
#define PCI_0CS_2_BANK_SIZE				0xd18
#define PCI_1CS_2_BANK_SIZE				0xd98
#define PCI_0CS_3_BANK_SIZE				0xc14
#define PCI_1CS_3_BANK_SIZE				0xc94
#define PCI_0CS_BOOT_BANK_SIZE				0xd14
#define PCI_1CS_BOOT_BANK_SIZE				0xd94
#define PCI_0P2P_MEM0_BAR_SIZE                          0xd1c
#define PCI_1P2P_MEM0_BAR_SIZE                          0xd9c
#define PCI_0P2P_MEM1_BAR_SIZE                          0xd20
#define PCI_1P2P_MEM1_BAR_SIZE                          0xda0
#define PCI_0P2P_I_O_BAR_SIZE                           0xd24
#define PCI_1P2P_I_O_BAR_SIZE                           0xda4
#define PCI_0CPU_BAR_SIZE                               0xd28
#define PCI_1CPU_BAR_SIZE                               0xda8
#define PCI_0DAC_SCS_0_BANK_SIZE                        0xe00
#define PCI_1DAC_SCS_0_BANK_SIZE                        0xe80
#define PCI_0DAC_SCS_1_BANK_SIZE                        0xe04
#define PCI_1DAC_SCS_1_BANK_SIZE                        0xe84
#define PCI_0DAC_SCS_2_BANK_SIZE                        0xe08
#define PCI_1DAC_SCS_2_BANK_SIZE                        0xe88
#define PCI_0DAC_SCS_3_BANK_SIZE                        0xe0c
#define PCI_1DAC_SCS_3_BANK_SIZE                        0xe8c
#define PCI_0DAC_CS_0_BANK_SIZE                         0xe10
#define PCI_1DAC_CS_0_BANK_SIZE                         0xe90
#define PCI_0DAC_CS_1_BANK_SIZE                         0xe14
#define PCI_1DAC_CS_1_BANK_SIZE                         0xe94
#define PCI_0DAC_CS_2_BANK_SIZE                         0xe18
#define PCI_1DAC_CS_2_BANK_SIZE                         0xe98
#define PCI_0DAC_CS_3_BANK_SIZE                         0xe1c
#define PCI_1DAC_CS_3_BANK_SIZE                         0xe9c
#define PCI_0DAC_BOOTCS_BANK_SIZE                       0xe20
#define PCI_1DAC_BOOTCS_BANK_SIZE                       0xea0
#define PCI_0DAC_P2P_MEM0_BAR_SIZE                      0xe24
#define PCI_1DAC_P2P_MEM0_BAR_SIZE                      0xea4
#define PCI_0DAC_P2P_MEM1_BAR_SIZE                      0xe28
#define PCI_1DAC_P2P_MEM1_BAR_SIZE                      0xea8
#define PCI_0DAC_CPU_BAR_SIZE                           0xe2c
#define PCI_1DAC_CPU_BAR_SIZE                           0xeac
#define PCI_0EXPANSION_ROM_BAR_SIZE                     0xd2c
#define PCI_1EXPANSION_ROM_BAR_SIZE                     0xdac
#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 		0xc3c
#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 		0xcbc
#define PCI_0SCS_0_BASE_ADDRESS_REMAP			0xc48
#define PCI_1SCS_0_BASE_ADDRESS_REMAP			0xcc8
#define PCI_0SCS_1_BASE_ADDRESS_REMAP			0xd48
#define PCI_1SCS_1_BASE_ADDRESS_REMAP			0xdc8
#define PCI_0SCS_2_BASE_ADDRESS_REMAP			0xc4c
#define PCI_1SCS_2_BASE_ADDRESS_REMAP			0xccc
#define PCI_0SCS_3_BASE_ADDRESS_REMAP			0xd4c
#define PCI_1SCS_3_BASE_ADDRESS_REMAP			0xdcc
#define PCI_0CS_0_BASE_ADDRESS_REMAP			0xc50
#define PCI_1CS_0_BASE_ADDRESS_REMAP			0xcd0
#define PCI_0CS_1_BASE_ADDRESS_REMAP			0xd50
#define PCI_1CS_1_BASE_ADDRESS_REMAP			0xdd0
#define PCI_0CS_2_BASE_ADDRESS_REMAP			0xd58
#define PCI_1CS_2_BASE_ADDRESS_REMAP			0xdd8
#define PCI_0CS_3_BASE_ADDRESS_REMAP           		0xc54
#define PCI_1CS_3_BASE_ADDRESS_REMAP           		0xcd4
#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP      		0xd54
#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP      		0xdd4
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xd5c
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xddc
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xd60
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xde0
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xd64
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xde4
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xd68
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xde8
#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP                 0xd6c
#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP                 0xdec
#define PCI_0CPU_BASE_ADDRESS_REMAP                     0xd70
#define PCI_1CPU_BASE_ADDRESS_REMAP                     0xdf0
#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP               0xf00
#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP               0xff0
#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP               0xf04
#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP               0xf84
#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP               0xf08
#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP               0xf88
#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP               0xf0c
#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP               0xf8c
#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP                0xf10
#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP                0xf90
#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP                0xf14
#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP                0xf94
#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP                0xf18
#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP                0xf98
#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP                0xf1c
#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP                0xf9c
#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP              0xf20
#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP                  0xfa0
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xf24
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xfa4
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xf28
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xfa8
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xf2c
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xfac
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xf30
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xfb0
#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP                     0xf34
#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP                     0xfb4
#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP               0xf38
#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP               0xfb8
#define PCI_0ADDRESS_DECODE_CONTROL                         0xd3c
#define PCI_1ADDRESS_DECODE_CONTROL                         0xdbc

/****************************************/
/* PCI Control                          */
/****************************************/

#define PCI_0COMMAND					    0xc00
#define PCI_1COMMAND					    0xc80
#define PCI_0MODE                                           0xd00
#define PCI_1MODE                                           0xd80
#define PCI_0TIMEOUT_RETRY				    0xc04
#define PCI_1TIMEOUT_RETRY				    0xc84
#define PCI_0READ_BUFFER_DISCARD_TIMER                      0xd04
#define PCI_1READ_BUFFER_DISCARD_TIMER                      0xd84
#define MSI_0TRIGGER_TIMER                                  0xc38
#define MSI_1TRIGGER_TIMER                                  0xcb8
#define PCI_0ARBITER_CONTROL                                0x1d00
#define PCI_1ARBITER_CONTROL                                0x1d80
/* changing untill here */
#define PCI_0CROSS_BAR_CONTROL_LOW                           0x1d08
#define PCI_0CROSS_BAR_CONTROL_HIGH                          0x1d0c
#define PCI_0CROSS_BAR_TIMEOUT                               0x1d04
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d18
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH            0x1d1c
#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d10
#define PCI_0P2P_CONFIGURATION                               0x1d14
#define PCI_0ACCESS_CONTROL_BASE_0_LOW                       0x1e00
#define PCI_0ACCESS_CONTROL_BASE_0_HIGH                      0x1e04
#define PCI_0ACCESS_CONTROL_TOP_0                            0x1e08
#define PCI_0ACCESS_CONTROL_BASE_1_LOW                       0c1e10
#define PCI_0ACCESS_CONTROL_BASE_1_HIGH                      0x1e14
#define PCI_0ACCESS_CONTROL_TOP_1                            0x1e18
#define PCI_0ACCESS_CONTROL_BASE_2_LOW                       0c1e20
#define PCI_0ACCESS_CONTROL_BASE_2_HIGH                      0x1e24
#define PCI_0ACCESS_CONTROL_TOP_2                            0x1e28
#define PCI_0ACCESS_CONTROL_BASE_3_LOW                       0c1e30
#define PCI_0ACCESS_CONTROL_BASE_3_HIGH                      0x1e34
#define PCI_0ACCESS_CONTROL_TOP_3                            0x1e38
#define PCI_0ACCESS_CONTROL_BASE_4_LOW                       0c1e40
#define PCI_0ACCESS_CONTROL_BASE_4_HIGH                      0x1e44
#define PCI_0ACCESS_CONTROL_TOP_4                            0x1e48
#define PCI_0ACCESS_CONTROL_BASE_5_LOW                       0c1e50
#define PCI_0ACCESS_CONTROL_BASE_5_HIGH                      0x1e54
#define PCI_0ACCESS_CONTROL_TOP_5                            0x1e58
#define PCI_0ACCESS_CONTROL_BASE_6_LOW                       0c1e60
#define PCI_0ACCESS_CONTROL_BASE_6_HIGH                      0x1e64
#define PCI_0ACCESS_CONTROL_TOP_6                            0x1e68
#define PCI_0ACCESS_CONTROL_BASE_7_LOW                       0c1e70
#define PCI_0ACCESS_CONTROL_BASE_7_HIGH                      0x1e74
#define PCI_0ACCESS_CONTROL_TOP_7                            0x1e78
#define PCI_1CROSS_BAR_CONTROL_LOW                           0x1d88
#define PCI_1CROSS_BAR_CONTROL_HIGH                          0x1d8c
#define PCI_1CROSS_BAR_TIMEOUT                               0x1d84
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d98
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH            0x1d9c
#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d90
#define PCI_1P2P_CONFIGURATION                               0x1d94
#define PCI_1ACCESS_CONTROL_BASE_0_LOW                       0x1e80
#define PCI_1ACCESS_CONTROL_BASE_0_HIGH                      0x1e84
#define PCI_1ACCESS_CONTROL_TOP_0                            0x1e88
#define PCI_1ACCESS_CONTROL_BASE_1_LOW                       0c1e90
#define PCI_1ACCESS_CONTROL_BASE_1_HIGH                      0x1e94
#define PCI_1ACCESS_CONTROL_TOP_1                            0x1e98
#define PCI_1ACCESS_CONTROL_BASE_2_LOW                       0c1ea0
#define PCI_1ACCESS_CONTROL_BASE_2_HIGH                      0x1ea4
#define PCI_1ACCESS_CONTROL_TOP_2                            0x1ea8
#define PCI_1ACCESS_CONTROL_BASE_3_LOW                       0c1eb0
#define PCI_1ACCESS_CONTROL_BASE_3_HIGH                      0x1eb4
#define PCI_1ACCESS_CONTROL_TOP_3                            0x1eb8
#define PCI_1ACCESS_CONTROL_BASE_4_LOW                       0c1ec0
#define PCI_1ACCESS_CONTROL_BASE_4_HIGH                      0x1ec4
#define PCI_1ACCESS_CONTROL_TOP_4                            0x1ec8
#define PCI_1ACCESS_CONTROL_BASE_5_LOW                       0c1ed0
#define PCI_1ACCESS_CONTROL_BASE_5_HIGH                      0x1ed4
#define PCI_1ACCESS_CONTROL_TOP_5                            0x1ed8
#define PCI_1ACCESS_CONTROL_BASE_6_LOW                       0c1ee0
#define PCI_1ACCESS_CONTROL_BASE_6_HIGH                      0x1ee4
#define PCI_1ACCESS_CONTROL_TOP_6                            0x1ee8
#define PCI_1ACCESS_CONTROL_BASE_7_LOW                       0c1ef0
#define PCI_1ACCESS_CONTROL_BASE_7_HIGH                      0x1ef4
#define PCI_1ACCESS_CONTROL_TOP_7                            0x1ef8

/****************************************/
/* PCI Snoop Control                    */
/****************************************/

#define PCI_0SNOOP_CONTROL_BASE_0_LOW                        0x1f00
#define PCI_0SNOOP_CONTROL_BASE_0_HIGH                       0x1f04
#define PCI_0SNOOP_CONTROL_TOP_0                             0x1f08
#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW                      0x1f10
#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f14
#define PCI_0SNOOP_CONTROL_TOP_1                             0x1f18
#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW                      0x1f20
#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH                     0x1f24
#define PCI_0SNOOP_CONTROL_TOP_2                             0x1f28
#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW                      0x1f30
#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH                     0x1f34
#define PCI_0SNOOP_CONTROL_TOP_3                             0x1f38
#define PCI_1SNOOP_CONTROL_BASE_0_LOW                        0x1f80
#define PCI_1SNOOP_CONTROL_BASE_0_HIGH                       0x1f84
#define PCI_1SNOOP_CONTROL_TOP_0                             0x1f88
#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW                      0x1f90
#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f94
#define PCI_1SNOOP_CONTROL_TOP_1                             0x1f98
#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW                      0x1fa0
#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH                     0x1fa4
#define PCI_1SNOOP_CONTROL_TOP_2                             0x1fa8
#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW                      0x1fb0
#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH                     0x1fb4
#define PCI_1SNOOP_CONTROL_TOP_3                             0x1fb8

/****************************************/
/* PCI Configuration Address            */
/****************************************/

#define PCI_0CONFIGURATION_ADDRESS 				0xcf8
#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xcfc
#define PCI_1CONFIGURATION_ADDRESS 				0xc78
#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xc7c
#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xc34
#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xcb4

/****************************************/
/* PCI Error Report                     */
/****************************************/

#define PCI_0SERR_MASK					 	0xc28
#define PCI_0ERROR_ADDRESS_LOW                               0x1d40
#define PCI_0ERROR_ADDRESS_HIGH                              0x1d44
#define PCI_0ERROR_DATA_LOW                                  0x1d48
#define PCI_0ERROR_DATA_HIGH                                 0x1d4c
#define PCI_0ERROR_COMMAND                                   0x1d50
#define PCI_0ERROR_CAUSE                                     0x1d58
#define PCI_0ERROR_MASK                                      0x1d5c
#define PCI_1SERR_MASK						 0xca8
#define PCI_1ERROR_ADDRESS_LOW                               0x1dc0
#define PCI_1ERROR_ADDRESS_HIGH                              0x1dc4
#define PCI_1ERROR_DATA_LOW                                  0x1dc8
#define PCI_1ERROR_DATA_HIGH                                 0x1dcc