cpc700.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#define	CPC700_PMM1HIGH		0xff40001c	/* PMM 1 PCI High Address */
#define	CPC700_PMM2ADDR		0xff400020	/* PMM 2 Local Address */
#define	CPC700_PMM2MASK		0xff400024	/* PMM 2 Mask/Attribute */
#define	CPC700_PMM2LO		0xff400028	/* PMM 2 PCI Low Address */
#define	CPC700_PMM2HIGH		0xff40002c	/* PMM 2 PCI High Address */
#define	CPC700_PTM1SIZE		0xff400030	/* PTM 1 Memory Size */
#define	CPC700_PTM1ADDR		0xff400034	/* PTM 1 Local Address */
#define	CPC700_PTM2SIZE		0xff400038	/* PTM 2 Memory Size */
#define	CPC700_PTM2ADDR		0xff40003c	/* PTM 2 Local Address */

/*
 * IIC interface.
 */
#define	CPC700_IIC0		0xff620000	/* IIC0 Base Address */
#define	CPC700_IIC1		0xff630000	/* IIC1 Base Address */
#define	CPC700_IIC0_MDBUF	0xff620000	/* IIC0 Master Data Buffer */
#define CPC700_IIC0_SDBUF	0xff620002	/* IIC0 Slave Data Buffer */
#define CPC700_IIC0_LMADR	0xff620004	/* IIC0 Low Master Address */
#define CPC700_IIC0_HMADR	0xff620005	/* IIC0 High Master Address */
#define CPC700_IIC0_CNTL	0xff620006	/* IIC0 Control */
#define CPC700_IIC0_MDCNTL	0xff620007	/* IIC0 Mode Control */
#define CPC700_IIC0_STS		0xff620008	/* IIC0 Status */
#define CPC700_IIC0_EXTSTS	0xff620009	/* IIC0 Extended Status */
#define CPC700_IIC0_LSADR	0xff62000a	/* IIC0 Low Slave Address */
#define CPC700_IIC0_HSADR	0xff62000b	/* IIC0 High Slave Address */
#define CPC700_IIC0_CLKDIV	0xff62000c	/* IIC0 Clock Divide */
#define CPC700_IIC0_INTRMASK	0xff62000d	/* IIC0 Interrupt Mask */
#define CPC700_IIC0_XFRCNT	0xff62000e	/* IIC0 Transfer Count */
#define CPC700_IIC0_XTCNTLSS	0xff62000f	/* IIC0 Extended Control & Slave Status */
#define CPC700_IIC0_DIRECTCNTL	0xff620010	/* IIC0 Direct Control */
#define CPC700_IIC1_MDBUF       0xff630000      /* IIC1 Master Data Buffer */
#define CPC700_IIC1_SDBUF       0xff630002      /* IIC1 Slave Data Buffer */
#define CPC700_IIC1_LMADR       0xff630004      /* IIC1 Low Master Address */
#define CPC700_IIC1_HMADR       0xff630005      /* IIC1 High Master Address */
#define CPC700_IIC1_CNTL        0xff630006      /* IIC1 Control */
#define CPC700_IIC1_MDCNTL      0xff630007      /* IIC1 Mode Control */
#define CPC700_IIC1_STS         0xff630008      /* IIC1 Status */
#define CPC700_IIC1_EXTSTS      0xff630009      /* IIC1 Extended Status */
#define CPC700_IIC1_LSADR       0xff63000a      /* IIC1 Low Slave Address */
#define CPC700_IIC1_HSADR       0xff63000b      /* IIC1 High Slave Address */
#define CPC700_IIC1_CLKDIV      0xff63000c      /* IIC1 Clock Divide */
#define CPC700_IIC1_INTRMASK    0xff63000d      /* IIC1 Interrupt Mask */
#define CPC700_IIC1_XFRCNT      0xff63000e      /* IIC1 Transfer Count */
#define CPC700_IIC1_XTCNTLSS    0xff63000f      /* IIC1 Extended Control & Slave Status */
#define CPC700_IIC1_DIRECTCNTL  0xff630010      /* IIC1 Direct Control */

#define	CPC700_IIC_MDBUF	0x00
#define	CPC700_IIC_SDBUF	0x02
#define	CPC700_IIC_LMADR	0x04
#define	CPC700_IIC_HMADR	0x05
#define	CPC700_IIC_CNTL		0x06
#define	CPC700_IIC_MDCNTL	0x07
#define	CPC700_IIC_STS		0x08
#define	CPC700_IIC_EXTSTS	0x09
#define	CPC700_IIC_LSADR	0x0a
#define	CPC700_IIC_HSADR	0x0b
#define	CPC700_IIC_CLKDIV	0x0c
#define	CPC700_IIC_INTRMSK	0x0d
#define	CPC700_IIC_XFRCNT	0x0e
#define	CPC700_IIC_XTCNTLSS	0x0f

/*
 *  I/O ports.
 */
#define CPC700_UART0RBR		0xff600300	/* UART 0 Receiver Buffer Register, DLAB=0 */
#define CPC700_UART0THR		0xff600300	/* UART 0 Transmitter Holding Register, DLAB=0 */
#define CPC700_UART0DLL		0xff600300	/* UART 0 Divisor Latch (LSB), DLAB=1 */
#define CPC700_UART0IER		0xff600301	/* UART 0 Interrupt Enable Register, DLAB=0  */
#define CPC700_UART0DLM		0xff600301	/* UART 0 Divisor Latch (MSB), DLAB=1 */
#define CPC700_UART0IIR		0xff600302	/* UART 0 Interrupt Identification Register */
#define CPC700_UART0FCR		0xff600302	/* UART 0 FIFO Control Register */
#define CPC700_UART0LCR		0xff600303	/* UART 0 Line Control Register */
#define CPC700_UART0MCR		0xff600304	/* UART 0 Modem Control Register */
#define CPC700_UART0LSR		0xff600305	/* UART 0 Line Status Register */
#define CPC700_UART0MSSR	0xff600306	/* UART 0 Modem Status Register */
#define CPC700_UART0SCR		0xff600307	/* UART 0 Scratch Register */
#define CPC700_UART1RBR         0xff600400      /* UART 1 Receiver Buffer Register, DLAB=0 */
#define CPC700_UART1THR         0xff600400      /* UART 1 Transmitter Holding Register, DLAB=0 */
#define CPC700_UART1DLL         0xff600400      /* UART 1 Divisor Latch (LSB), DLAB=1 */
#define CPC700_UART1IER         0xff600401      /* UART 1 Interrupt Enable Register, DLAB=0  */
#define CPC700_UART1DLM         0xff600401      /* UART 1 Divisor Latch (MSB), DLAB=1 */
#define CPC700_UART1IIR         0xff600402      /* UART 1 Interrupt Identification Register */ 
#define CPC700_UART1FCR         0xff600402      /* UART 1 FIFO Control Register */
#define CPC700_UART1LCR         0xff600403      /* UART 1 Line Control Register */
#define CPC700_UART1MCR         0xff600404      /* UART 1 Modem Control Register */
#define CPC700_UART1LSR         0xff600405      /* UART 1 Line Status Register */
#define CPC700_UART1MSSR        0xff600406      /* UART 1 Modem Status Register */
#define CPC700_UART1SCR         0xff600407      /* UART 1 Scratch Register */

/*
 * Bus Support
 */
#define CPC700_PESRRD		0xff500850	/* PLB Error Status Register (read/clear) */
#define CPC700_PERRWR		0xff500854	/* PLB Error Status Register (set) */
#define CPC700_PACR		0xff50085c	/* PLB Arbiter Control Register */
#define CPC700_GESRRD		0xff500810	/* OPB Bridge Error Status Register (read/clear) */
#define CPC700_GESRWR		0xff500814	/* OPB Bridge Error Status Register (set) */
#define CPC700_GEAR		0xff500818	/* OPB Bridge Error Address Register */

/*
 * Universal Interrupt Controller
 */
#define CPC700_UICSR		0xff500880	/* UIC Status Register (read/clear) */
#define CPC700_UICSRS		0xff500884	/* UIC Status Register (set) */
#define CPC700_UICER		0xff500888	/* UIC Enable Register */
#define CPC700_UICCR		0xff50088c	/* UIC Critical Register */
#define CPC700_UICPR		0xff500890	/* UIC Polarity Register */
#define CPC700_UICTR		0xff500894	/* UIC Trigger Register */
#define CPC700_UICMSR		0xff500898	/* UIC Masked Status Register */
#define CPC700_UICVR		0xff50089c	/* UIC Vector Register */
#define CPC700_UICVCR		0xff5008a0	/* UIC Vector Configuration Register */

/*
 * General Purpose Timers
 */
#define CPC700_GPTTBC		0xff650000	/* GPT Time Base Counter */
#define CPC700_GPTCE		0xff650004	/* Capture Timers Enable */
#define CPC700_GPTEC		0xff650008	/* Capture Events Edge Detection Control */
#define CPC700_GPTSC		0xff65000c	/* Capture Events Synchronization Control */
#define CPC700_GPTIE		0xff650018	/* Timers Interrupt Enable */
#define CPC700_GPTIS		0xff65001c	/* Timers Interrupt Status */
#define CPC700_GPTISR		0xff650020	/* Timers Interrupt Status (clear upon read) */
#define CPC700_GPTIM		0xff650024	/* Timers Interrupt Mask */
#define CPC700_GPTCAPT0		0xff650040	/* Capture Timer 0 */
#define CPC700_GPTCAPT1         0xff650044      /* Capture Timer 1 */
#define CPC700_GPTCAPT2         0xff650048      /* Capture Timer 2 */
#define CPC700_GPTCAPT3         0xff65004c      /* Capture Timer 3 */
#define CPC700_GPTCAPT4         0xff650050      /* Capture Timer 4 */
#define CPC700_GPTCOMP0		0xff650080	/* Compare Timer 0 */
#define CPC700_GPTCOMP1         0xff650084      /* Compare Timer 1 */
#define CPC700_GPTCOMP2         0xff650088      /* Compare Timer 2 */
#define CPC700_GPTCOMP3         0xff65008c      /* Compare Timer 3 */
#define CPC700_GPTCOMP4         0xff650090      /* Compare Timer 4 */
#define CPC700_GPTMASK0		0xff65000c0	/* TBC Mask (Compare Timer 0) */
#define CPC700_GPTMASK1         0xff65000c4     /* TBC Mask (Compare Timer 1) */
#define CPC700_GPTMASK2         0xff65000c8     /* TBC Mask (Compare Timer 2) */
#define CPC700_GPTMASK3         0xff65000cc     /* TBC Mask (Compare Timer 3) */
#define CPC700_GPTMASK4         0xff65000d0     /* TBC Mask (Compare Timer 4) */

/*
 * CPR Registers
 */
#define CPC700_CRPRMCTRL	0xff500900	/* Peripheral Power Management Control */
#define CPC700_CPRRESET		0xff500904	/* Peripheral Reset Control */
#define CPC700_CPRCAPTEVNT	0xff500908	/* GPT Capture Event Generation */
#define CPC700_CPRPLLACCESS	0xff50090c	/* PLL Configureation Access Register (unlocks CPRPLLTUNE) */
#define CPC700_CPRPLLTUNE	0xff500910	/* PLL Configuration Register (resets system upon write) */
#define CPC700_CPRSTRAPREAD	0xff500914	/* Strapping Pin Status Read Register */


/*
 * CPC700 Memory Map
 */
#define	CPC700_PCI_MEM_BASE	0x80000000
#define	CPC700_PCI_MEM_SIZE	0x78000000
#define	CPC700_PCI_IO_BASE	0xf8000000
#define	CPC700_PCI_IO_SIZE	0x00010000
#define CPC700_PCI_IO_REMAP	0x00000000
#define	CPC700_PCI_IO2_BASE	0xf8800000
#define	CPC700_PCI_IO2_SIZE	0x03800000
#define CPC700_PCI_IO2_REMAP	0x00800000
#define CPC700_IO_BASE		0xfec00000
#define CPC700_IO_SIZE		0x00c00000

#ifdef __ASSEMBLER__
/*
 *  Macro used to setup CPC700 memory control.
 */
#define IORDER          eieio; sync

#define CPC700_MEM_SETUP(reg, val, mask)	\
	li 3, reg ; stw	3, 0(1) ; IORDER ;	\
	lwz	4, 0(2)	;			\
	lis 3, HI(mask); ori 3, 3, LO(mask) ;	\
	and 4, 4, 3 ;				\
	lis 3, HI(val) ; ori 3, 3, LO(val) ;	\
	or 4, 4, 3 ; stw 4, 0(2) ; IORDER

#define CPC700_MEM_RSETUP(reg, rval)    	\
	li 3, reg ; stw 3, 0(1) ; IORDER ;	\
	stw rval, 0(2) ; IORDER

#endif /* __ASSEMBLER__ */
#endif /* __CPC700_H__ */