cpc700.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: cpc700.h,v 1.3 2001/12/20 07:54:04 pefo Exp $ */

/*
 * Copyright (c) 2001 IP Unplugged AB   (www.ipunplugged.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for IP Unplugged AB, by
 *	Patrik Lindergren.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef __CPC700_H__
#define __CPC700_H__

/*
 * CPC700 bit definitions
 */
#define CPC700_BBIT0   0x80
#define CPC700_BBIT1   0x40
#define CPC700_BBIT2   0x20
#define CPC700_BBIT3   0x10
#define CPC700_BBIT4   0x08
#define CPC700_BBIT5   0x04
#define CPC700_BBIT6   0x02
#define CPC700_BBIT7   0x01

#define CPC700_WBIT0   0x8000
#define CPC700_WBIT1   0x4000
#define CPC700_WBIT2   0x2000
#define CPC700_WBIT3   0x1000
#define CPC700_WBIT4   0x0800
#define CPC700_WBIT5   0x0400
#define CPC700_WBIT6   0x0200
#define CPC700_WBIT7   0x0100
#define CPC700_WBIT8   0x0080
#define CPC700_WBIT9   0x0040
#define CPC700_WBIT10  0x0020
#define CPC700_WBIT11  0x0010
#define CPC700_WBIT12  0x0008
#define CPC700_WBIT13  0x0004
#define CPC700_WBIT14  0x0002
#define CPC700_WBIT15  0x0001

#define CPC700_LBIT0   0x80000000
#define CPC700_LBIT1   0x40000000
#define CPC700_LBIT2   0x20000000
#define CPC700_LBIT3   0x10000000
#define CPC700_LBIT4   0x08000000
#define CPC700_LBIT5   0x04000000
#define CPC700_LBIT6   0x02000000
#define CPC700_LBIT7   0x01000000
#define CPC700_LBIT8   0x00800000
#define CPC700_LBIT9   0x00400000
#define CPC700_LBIT10  0x00200000
#define CPC700_LBIT11  0x00100000
#define CPC700_LBIT12  0x00080000
#define CPC700_LBIT13  0x00040000
#define CPC700_LBIT14  0x00020000
#define CPC700_LBIT15  0x00010000
#define CPC700_LBIT16  0x00008000
#define CPC700_LBIT17  0x00004000
#define CPC700_LBIT18  0x00002000
#define CPC700_LBIT19  0x00001000
#define CPC700_LBIT20  0x00000800
#define CPC700_LBIT21  0x00000400
#define CPC700_LBIT22  0x00000200
#define CPC700_LBIT23  0x00000100
#define CPC700_LBIT24  0x00000080
#define CPC700_LBIT25  0x00000040
#define CPC700_LBIT26  0x00000020
#define CPC700_LBIT27  0x00000010
#define CPC700_LBIT28  0x00000008
#define CPC700_LBIT29  0x00000004
#define CPC700_LBIT30  0x00000002
#define CPC700_LBIT31  0x00000001

/*
 * CPC700 Processor Interface Registers
 */
#define CPC700_PIFCFGADR	0xff500000	/* Processor Interface Configuration Address Register */
#define CPC700_PIFCFGDATA	0xff500004 	/* Processor Interface Configuration Data Register */
#define CPC700_PRIOPT1		0x00 		/* Processor Interface Options 1 */
#define CPC700_ERRDET1		0x04 		/* Error Detection 1 */
#define CPC700_ERREN1		0x08		/* Error Detect Enable 1 */
#define CPC700_CPUERAD		0x0c		/* Processor Error Address */
#define CPC700_CPUERAT		0x10		/* Processor Error Attributes */
#define CPC700_PLBMIFOPT	0x18		/* Processor-PLB Master Interface Options */
#define CPC700_PLBMTLSA1	0x20		/* Processor-PLB Master Byte Swap Region 1 Starting Address */
#define CPC700_PLBMTLEA1	0x24		/* Processor-PLB Master Byte Swap Region 1 Ending Address */
#define CPC700_PLBMTLSA2	0x28		/* Processor-PLB Master Byte Swap Region 2 Starting Address */
#define CPC700_PLBMTLEA2	0x2c		/* Processor-PLB Master Byte Swap Region 2 Ending Address */
#define CPC700_PLBMTLSA3	0x30		/* Processor-PLB Master Byte Swap Region 3 Starting Address */
#define CPC700_PLBMTLEA3	0x34		/* Processor-PLB Master Byte Swap Region 3 Ending Address */
#define CPC700_PLBSNSSA0	0x38		/* PLB Slave No Snoop Region Starting Address */
#define CPC700_PLBSNSEA0	0x3c		/* PLB Slave No Snoop Region Ending Address */
#define CPC700_BESR		0x40		/* PLB Bus Error Syndrome Register */
#define CPC700_BESRSET		0x44		/* PLB Bus Error Syndrome Register Set (for test/verification use) */
#define CPC700_BEAR		0x4c		/* PCI Bus Master Error Address Register */
#define CPC700_PLBSWRINT	0x80		/* Write Interrupt Region Base Address */

/*
 *  CPC700 PCI addresses.
 */
#define	CPC700_PCICFGADDR	0xfec00000	/* PCI Configuration Address Register */
#define	CPC700_PCICFGDATA	0xfec00004	/* PCI Configuration Data Register */
#define	CPC700_PCI_CMD		0x04		/* Really pci config space */
#define	CPC700_PCI_STAT		0x06		/* Status Register */
#define	CPC700_PCI_REV		0x08		/* Revision ID */
#define CPC700_PCIPTM1BAR	0x14		/* PTM 1 BAR */
#define CPC700_PCIPTM2BAR	0x18		/* PTM 2 BAR */
#define CPC700_PCIBUSNUM	0x40
#define CPC700_PCISUBBUSNUM	0x41
#define CPC700_PCIDSCCNT	0x42		/* Disconnect Counter */
#define CPC700_PCIARBCNTL	0x44		/* PCI Arbiter Control */
#define CPC700_PCIERREN		0x48
#define CPC700_PCIERRSTS	0x49
#define CPC700_PCIBRDGOPT1	0x4a
#define CPC700_SESR		0x4c
#define CPC700_SEAR0		0x50
#define CPC700_SEAR1		0x54
#define CPC700_PCIBRDGOPT2	0x60

/*
 * CPC700 Memory Controller addresses
 */
#define	CPC700_MEMCFGADDR	0xff500008	/* Memory Controller Address */
#define	CPC700_MEMCFGDATA	0xff50000c	/* Memory Controller Data */
#define	CPC700_MCOPT1		0x20		/* Memory Contoller Options 1 */
#define	CPC700_MBEN		0x24		/* Memory Bank Enable */
#define	CPC700_MEMTYPE		0x28		/* Installed Memory Type */
#define CPC700_RWD		0x2c		/* Bank Active Watchdog Timer */
#define	CPC700_RTR		0x30		/* Refresh Timer Register */
#define	CPC700_DAM		0x34		/* DRAM Addressing Mode */
#define	CPC700_MB0SA		0x38		/* Memory Bank 0 Starting Address */
#define	CPC700_MB1SA		0x3c		/* Memory Bank 1 Stating Address */
#define	CPC700_MB2SA		0x40		/* Memory Bank 2 Starting Address */
#define	CPC700_MB3SA		0x44		/* Memory Bank 3 Starting Address */
#define	CPC700_MB4SA		0x48		/* Memory Bank 4 Starting Address */
#define	CPC700_MB0EA		0x58		/* Memory Bank 0 Ending Address */
#define	CPC700_MB1EA		0x5c		/* Memory Bank 1 Ending Address */
#define	CPC700_MB2EA		0x60		/* Memory Bank 2 Ending Address */
#define	CPC700_MB3EA		0x64		/* Memory Bank 3 Ending Address */
#define	CPC700_MB4EA		0x68		/* Memory Bank 4 Ending Address */
#define	CPC700_SDTR1		0x80		/* SDRAM Timing Register 1 */
#define	CPC700_RBW		0x88		/* ROM Bank Width */
#define	CPC700_FWEN		0x90		/* Flash Write Enable */
#define	CPC700_ECCCF		0x94		/* ECC Configuration */
#define CPC700_ECCERR		0x98		/* ECC Error */
#define CPC700_RPB0P		0xe0		/* ROM / Peripheral Bank 0 Parameters */
#define	CPC700_RPB1P		0xe4		/* ROM / Peripheral Bank 1 Parameters */
#define CPC700_RPB2P		0xe8		/* ROM / Peripheral Bank 2 Parameters */
#define CPC700_RPB3P		0xec		/* ROM / Peripheral Bank 3 Parameters */
#define	CPC700_RPB4P		0xf0		/* ROM / Peripheral Bank 4 Parameters */

/* PCI to local bus configuration */
#define	CPC700_PMM0ADDR		0xff400000	/* PMM 0 Local Address */
#define	CPC700_PMM0MASK		0xff400004	/* PMM 0 Mask/Attribute */
#define	CPC700_PMM0LO		0xff400008	/* PMM 0 PCI Low Address */
#define	CPC700_PMM0HIGH		0xff40000c	/* PMM 0 PCI High Address */
#define	CPC700_PMM1ADDR		0xff400010	/* PMM 1 Local Address */
#define	CPC700_PMM1MASK		0xff400014	/* PMM 1 Mask/Attribute */
#define	CPC700_PMM1LO		0xff400018	/* PMM 1 PCI Low Address */