mv64460reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#define PCI_STATUS_AND_COMMAND				0x004
#define PCI_CLASS_CODE_AND_REVISION_ID		        0x008
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	0x00C

#define PCI_SCS_0_BASE_ADDR_LOW   		        0x010
#define PCI_SCS_0_BASE_ADDR_HIGH   		        0x014
#define PCI_SCS_1_BASE_ADDR_LOW  		        0x018
#define PCI_SCS_1_BASE_ADDR_HIGH  		        0x01C
#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LO       	0x020
#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH     	0x024
#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	0x02c
#define PCI_EXPANSION_ROM_BASE_ADDR_REG		        0x030
#define PCI_CAPABILTY_LIST_POINTER                      0x034
#define PCI_INTERRUPT_PIN_AND_LINE 			0x03C
       /* capability list */
#define PCI_POWER_MANAGEMENT_CAPABILITY                 0x040
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL         0x044
#define PCI_VPD_ADDR                                    0x048
#define PCI_VPD_DATA                                    0x04c
#define PCI_MSI_MESSAGE_CONTROL                         0x050
#define PCI_MSI_MESSAGE_ADDR                            0x054
#define PCI_MSI_MESSAGE_UPPER_ADDR                      0x058
#define PCI_MSI_MESSAGE_DATA                            0x05c
#define PCI_X_COMMAND                                   0x060
#define PCI_X_STATUS                                    0x064
#define PCI_COMPACT_PCI_HOT_SWAP                        0x068

/***********************************************/
/*   PCI Configuration, Function 1, Registers  */
/***********************************************/

#define PCI_SCS_2_BASE_ADDR_LOW   			0x110
#define PCI_SCS_2_BASE_ADDR_HIGH			0x114
#define PCI_SCS_3_BASE_ADDR_LOW 			0x118
#define PCI_SCS_3_BASE_ADDR_HIGH			0x11c
#define PCI_INTERGRATED_SRAM_BASE_ADDR_LOW          	0x120
#define PCI_INTERGRATED_SRAM_BASE_ADDR_HIGH         	0x124

/***********************************************/
/*  PCI Configuration, Function 2, Registers   */
/***********************************************/

#define PCI_DEVCS_0_BASE_ADDR_LOW	    		0x210
#define PCI_DEVCS_0_BASE_ADDR_HIGH 			0x214
#define PCI_DEVCS_1_BASE_ADDR_LOW 			0x218
#define PCI_DEVCS_1_BASE_ADDR_HIGH      		0x21c
#define PCI_DEVCS_2_BASE_ADDR_LOW 			0x220
#define PCI_DEVCS_2_BASE_ADDR_HIGH      		0x224

/***********************************************/
/*  PCI Configuration, Function 3, Registers   */
/***********************************************/

#define PCI_DEVCS_3_BASE_ADDR_LOW	    		0x310
#define PCI_DEVCS_3_BASE_ADDR_HIGH 			0x314
#define PCI_BOOT_CS_BASE_ADDR_LOW			0x318
#define PCI_BOOT_CS_BASE_ADDR_HIGH      		0x31c
#define PCI_CPU_BASE_ADDR_LOW 				0x220
#define PCI_CPU_BASE_ADDR_HIGH      			0x224

/***********************************************/
/*  PCI Configuration, Function 4, Registers   */
/***********************************************/

#define PCI_P2P_MEM0_BASE_ADDR_LOW  			0x410
#define PCI_P2P_MEM0_BASE_ADDR_HIGH 			0x414
#define PCI_P2P_MEM1_BASE_ADDR_LOW   			0x418
#define PCI_P2P_MEM1_BASE_ADDR_HIGH 			0x41c
#define PCI_P2P_I_O_BASE_ADDR                 	        0x420
#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR          0x424

/****************************************/
/* Messaging Unit Registers (I20)   	*/
/****************************************/

#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		0x010
#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE  		0x014
#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 		0x018
#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE  		0x01C
#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE  		0x020
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE      0x024
#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	0x028
#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 		0x02C
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE     0x030
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE      0x034
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE   0x040
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE  0x044
#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 		0x050
#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 		0x054
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE    0x060
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE    0x064
#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE    0x068
#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE    0x06C
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE   0x070
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE   0x074
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE   0x0F8
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE   0x0FC

#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		0x090
#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE  		0x094
#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 		0x098
#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE  		0x09C
#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE  		0x0A0
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE      0x0A4
#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	0x0A8
#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 		0x0AC
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE     0x0B0
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE      0x0B4
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE   0x0C0
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE  0x0C4
#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 		0x0D0
#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 		0x0D4
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE    0x0E0
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE    0x0E4
#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE    0x0E8
#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE    0x0EC
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE   0x0F0
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE   0x0F4
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE   0x078
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE   0x07C

#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		0x1C10
#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE  		0x1C14
#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 		0x1C18
#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE  		0x1C1C
#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE  		0x1C20
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE  	0x1C24
#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	0x1C28
#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 		0x1C2C
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE      0x1C30
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE       0x1C34
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE    0x1C40
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE   0x1C44
#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE 		0x1C50
#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 		0x1C54
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE     0x1C60
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE     0x1C64
#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE     0x1C68
#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE     0x1C6C
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE    0x1C70
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE    0x1C74
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE    0x1CF8
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE    0x1CFC
#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		0x1C90
#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE  		0x1C94
#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 		0x1C98
#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE  		0x1C9C
#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE  		0x1CA0
#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE  	0x1CA4
#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	0x1CA8
#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 		0x1CAC
#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE      0x1CB0
#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE       0x1CB4
#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE    0x1CC0
#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE   0x1CC4
#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE 		0x1CD0
#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 		0x1CD4
#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE     0x1CE0
#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE     0x1CE4
#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE     0x1CE8
#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE     0x1CEC
#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE    0x1CF0
#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE    0x1CF4
#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE    0x1C78
#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE    0x1C7C

/****************************************/
/*        Ethernet Unit Registers  		*/
/****************************************/

#define ETH_PHY_ADDR_REG                                     0x2000
#define ETH_SMI_REG                                          0x2004
#define ETH_UNIT_DEFAULT_ADDR_REG                            0x2008
#define ETH_UNIT_DEFAULTID_REG                               0x200c
#define ETH_UNIT_INTERRUPT_CAUSE_REG                         0x2080
#define ETH_UNIT_INTERRUPT_MASK_REG                          0x2084
#define ETH_UNIT_INTERNAL_USE_REG                            0x24fc
#define ETH_UNIT_ERROR_ADDR_REG                              0x2094
#define ETH_BAR_0                                            0x2200
#define ETH_BAR_1                                            0x2208
#define ETH_BAR_2                                            0x2210
#define ETH_BAR_3                                            0x2218
#define ETH_BAR_4                                            0x2220
#define ETH_BAR_5                                            0x2228
#define ETH_SIZE_REG_0                                       0x2204
#define ETH_SIZE_REG_1                                       0x220c
#define ETH_SIZE_REG_2                                       0x2214
#define ETH_SIZE_REG_3                                       0x221c
#define ETH_SIZE_REG_4                                       0x2224
#define ETH_SIZE_REG_5                                       0x222c
#define ETH_HEADERS_RETARGET_BASE_REG                        0x2230
#define ETH_HEADERS_RETARGET_CONTROL_REG                     0x2234
#define ETH_HIGH_ADDR_REMAP_REG_0                            0x2280
#define ETH_HIGH_ADDR_REMAP_REG_1                            0x2284
#define ETH_HIGH_ADDR_REMAP_REG_2                            0x2288
#define ETH_HIGH_ADDR_REMAP_REG_3                            0x228c
#define ETH_BASE_ADDR_ENABLE_REG                             0x2290
#define ETH_ACCESS_PROTECTION_REG(port)                    (0x2294 + (port<<2))
#define ETH_MIB_COUNTERS_BASE(port)                        (0x3000 + (port<<7))
#define ETH_PORT_CONFIG_REG(port)                          (0x2400 + (port<<10))
#define ETH_PORT_CONFIG_EXTEND_REG(port)                   (0x2404 + (port<<10))
#define ETH_MII_SERIAL_PARAMETRS_REG(port)                 (0x2408 + (port<<10))
#define ETH_GMII_SERIAL_PARAMETRS_REG(port)                (0x240c + (port<<10))
#define ETH_VLAN_ETHERTYPE_REG(port)                       (0x2410 + (port<<10))
#define ETH_MAC_ADDR_LOW(port)                             (0x2414 + (port<<10))
#define ETH_MAC_ADDR_HIGH(port)                            (0x2418 + (port<<10))
#define ETH_SDMA_CONFIG_REG(port)                          (0x241c + (port<<10))
#define ETH_DSCP_0(port)                                   (0x2420 + (port<<10))
#define ETH_DSCP_1(port)                                   (0x2424 + (port<<10))
#define ETH_DSCP_2(port)                                   (0x2428 + (port<<10))
#define ETH_DSCP_3(port)                                   (0x242c + (port<<10))
#define ETH_DSCP_4(port)                                   (0x2430 + (port<<10))
#define ETH_DSCP_5(port)                                   (0x2434 + (port<<10))
#define ETH_DSCP_6(port)                                   (0x2438 + (port<<10))
#define ETH_PORT_SERIAL_CONTROL_REG(port)                  (0x243c + (port<<10))
#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)            (0x2440 + (port<<10))
#define ETH_PORT_STATUS_REG(port)                          (0x2444 + (port<<10))
#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)               (0x2448 + (port<<10))
#define ETH_TX_QUEUE_FIXED_PRIORITY(port)                  (0x244c + (port<<10))
#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)         (0x2450 + (port<<10))
#define ETH_MAXIMUM_TRANSMIT_UNIT(port)                    (0x2458 + (port<<10))
#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)           (0x245c + (port<<10))
#define ETH_INTERRUPT_CAUSE_REG(port)                      (0x2460 + (port<<10))
#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)               (0x2464 + (port<<10))
#define ETH_INTERRUPT_MASK_REG(port)                       (0x2468 + (port<<10))
#define ETH_INTERRUPT_EXTEND_MASK_REG(port)                (0x246c + (port<<10))
#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)             (0x2470 + (port<<10))
#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)             (0x2474 + (port<<10))
#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)                (0x247c + (port<<10))
#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)              (0x2484 + (port<<10))
#define ETH_PORT_DEBUG_0_REG(port)                         (0x248c + (port<<10))
#define ETH_PORT_DEBUG_1_REG(port)                         (0x2490 + (port<<10))
#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)             (0x2494 + (port<<10))
#define ETH_INTERNAL_USE_REG(port)                         (0x24fc + (port<<10))
#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)                (0x2680 + (port<<10))
#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)               (0x2684 + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)              (0x260c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)              (0x261c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)              (0x262c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)              (0x263c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)              (0x264c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)              (0x265c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)              (0x266c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)              (0x267c + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)              (0x26c0 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)              (0x26c4 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)              (0x26c8 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)              (0x26cc + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)              (0x26d0 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)              (0x26d4 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)              (0x26d8 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)              (0x26dc + (port<<10))
#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)            (0x2700 + (port<<10))
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)            (0x2710 + (port<<10))
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)            (0x2720 + (port<<10))
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)            (0x2730 + (port<<10))
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)            (0x2740 + (port<<10))
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)            (0x2750 + (port<<10))
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)            (0x2760 + (port<<10))
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)            (0x2770 + (port<<10))
#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)           (0x2704 + (port<<10))
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)           (0x2714 + (port<<10))
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)           (0x2724 + (port<<10))
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)           (0x2734 + (port<<10))
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)           (0x2744 + (port<<10))
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)           (0x2754 + (port<<10))
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)           (0x2764 + (port<<10))
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)           (0x2774 + (port<<10))
#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)                (0x2708 + (port<<10))
#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)                (0x2718 + (port<<10))
#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)                (0x2728 + (port<<10))
#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)                (0x2738 + (port<<10))
#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)                (0x2748 + (port<<10))
#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)                (0x2758 + (port<<10))
#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)                (0x2768 + (port<<10))