mv64460reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#define EXTENDED_DRAM_MODE                                  0x1420
#define SDRAM_CROSS_BAR_CONTROL_LOW                         0x1430
#define SDRAM_CROSS_BAR_CONTROL_HIGH                        0x1434
#define SDRAM_CROSS_BAR_TIMEOUT                             0x1438

#define	SDRAM_DATA_PADS_CALIBRATION			0x14c4

/****************************************/
/* SDRAM Error Report                   */
/****************************************/

#define SDRAM_ERROR_DATA_LOW                                0x1444
#define SDRAM_ERROR_DATA_HIGH                               0x1440
#define SDRAM_ERROR_ADDR                                    0x1450
#define SDRAM_RECEIVED_ECC                                  0x1448
#define SDRAM_CALCULATED_ECC                                0x144c
#define SDRAM_ECC_CONTROL                                   0x1454
#define SDRAM_ECC_ERROR_COUNTER                             0x1458

/******************************************/
/*  Controlled Delay Line (CDL) Registers */
/******************************************/

#define DFCDL_CONFIG0                                       0x1480
#define DFCDL_CONFIG1                                       0x1484
#define DLL_WRITE                                           0x1488
#define DLL_READ                                            0x148c
#define SRAM_ADDR                                           0x1490
#define SRAM_DATA0                                          0x1494
#define SRAM_DATA1                                          0x1498
#define SRAM_DATA2                                          0x149c
#define DFCL_PROBE                                          0x14a0

/******************************************/
/*   Debug Registers                      */
/******************************************/

#define DUNIT_DEBUG_LOW                                     0x1460
#define DUNIT_DEBUG_HIGH                                    0x1464
#define DUNIT_MMASK                                         0X1b40

/****************************************/
/* Device Parameters					*/
/****************************************/

#define DEVICE_BANK0_PARAMETERS				0x45c
#define DEVICE_BANK1_PARAMETERS				0x460
#define DEVICE_BANK2_PARAMETERS				0x464
#define DEVICE_BANK3_PARAMETERS				0x468
#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
#define DEVICE_INTERFACE_CONTROL                        0x4c0
#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW          0x4c8
#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH         0x4cc
#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT              0x4c4

/****************************************/
/* Device interrupt registers			*/
/****************************************/

#define DEVICE_INTERRUPT_CAUSE				0x4d0
#define DEVICE_INTERRUPT_MASK				0x4d4
#define DEVICE_ERROR_ADDR				0x4d8
#define DEVICE_ERROR_DATA   				0x4dc
#define DEVICE_ERROR_PARITY     			0x4e0

/****************************************/
/* Device debug registers   			*/
/****************************************/

#define DEVICE_DEBUG_LOW     			        0x4e4
#define DEVICE_DEBUG_HIGH     			        0x4e8
#define RUNIT_MMASK					0x4f0

/****************************************/
/* PCI Slave Address Decoding registers */
/****************************************/

#define PCI_0_CS_0_BANK_SIZE                            0xc08
#define PCI_1_CS_0_BANK_SIZE                            0xc88
#define PCI_0_CS_1_BANK_SIZE                            0xd08
#define PCI_1_CS_1_BANK_SIZE                            0xd88
#define PCI_0_CS_2_BANK_SIZE                            0xc0c
#define PCI_1_CS_2_BANK_SIZE                            0xc8c
#define PCI_0_CS_3_BANK_SIZE                            0xd0c
#define PCI_1_CS_3_BANK_SIZE                            0xd8c
#define PCI_0_DEVCS_0_BANK_SIZE                         0xc10
#define PCI_1_DEVCS_0_BANK_SIZE                         0xc90
#define PCI_0_DEVCS_1_BANK_SIZE                         0xd10
#define PCI_1_DEVCS_1_BANK_SIZE                         0xd90
#define PCI_0_DEVCS_2_BANK_SIZE                         0xd18
#define PCI_1_DEVCS_2_BANK_SIZE                         0xd98
#define PCI_0_DEVCS_3_BANK_SIZE                         0xc14
#define PCI_1_DEVCS_3_BANK_SIZE                         0xc94
#define PCI_0_DEVCS_BOOT_BANK_SIZE                      0xd14
#define PCI_1_DEVCS_BOOT_BANK_SIZE                      0xd94
#define PCI_0_P2P_MEM0_BAR_SIZE                         0xd1c
#define PCI_1_P2P_MEM0_BAR_SIZE                         0xd9c
#define PCI_0_P2P_MEM1_BAR_SIZE                         0xd20
#define PCI_1_P2P_MEM1_BAR_SIZE                         0xda0
#define PCI_0_P2P_I_O_BAR_SIZE                          0xd24
#define PCI_1_P2P_I_O_BAR_SIZE                          0xda4
#define PCI_0_CPU_BAR_SIZE                              0xd28
#define PCI_1_CPU_BAR_SIZE                              0xda8
#define PCI_0_INTEGRATED_SRAM_BAR_SIZE                  0xe00
#define PCI_1_INTEGRATED_SRAM_BAR_SIZE                  0xe80
#define PCI_0_EXPANSION_ROM_BAR_SIZE                    0xd2c
#define PCI_1_EXPANSION_ROM_BAR_SIZE                    0xd9c
#define PCI_0_BASE_ADDR_REG_ENABLE                      0xc3c
#define PCI_1_BASE_ADDR_REG_ENABLE                      0xcbc
#define PCI_0_CS_0_BASE_ADDR_REMAP		        0xc48
#define PCI_1_CS_0_BASE_ADDR_REMAP		        0xcc8
#define PCI_0_CS_1_BASE_ADDR_REMAP		        0xd48
#define PCI_1_CS_1_BASE_ADDR_REMAP		        0xdc8
#define PCI_0_CS_2_BASE_ADDR_REMAP		        0xc4c
#define PCI_1_CS_2_BASE_ADDR_REMAP		        0xccc
#define PCI_0_CS_3_BASE_ADDR_REMAP		        0xd4c
#define PCI_1_CS_3_BASE_ADDR_REMAP		        0xdcc
#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP		        0xF04
#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP		        0xF84
#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP		        0xF08
#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP		        0xF88
#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP		        0xF0C
#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP		        0xF8C
#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP		        0xF10
#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP		        0xF90
#define PCI_0_DEVCS_0_BASE_ADDR_REMAP		        0xc50
#define PCI_1_DEVCS_0_BASE_ADDR_REMAP		        0xcd0
#define PCI_0_DEVCS_1_BASE_ADDR_REMAP		        0xd50
#define PCI_1_DEVCS_1_BASE_ADDR_REMAP		        0xdd0
#define PCI_0_DEVCS_2_BASE_ADDR_REMAP		        0xd58
#define PCI_1_DEVCS_2_BASE_ADDR_REMAP		        0xdd8
#define PCI_0_DEVCS_3_BASE_ADDR_REMAP           	0xc54
#define PCI_1_DEVCS_3_BASE_ADDR_REMAP           	0xcd4
#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP      	0xd54
#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP      	0xdd4
#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW              0xd5c
#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW              0xddc
#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH             0xd60
#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH             0xde0
#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW              0xd64
#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW              0xde4
#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH             0xd68
#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH             0xde8
#define PCI_0_P2P_I_O_BASE_ADDR_REMAP                   0xd6c
#define PCI_1_P2P_I_O_BASE_ADDR_REMAP                   0xdec 
#define PCI_0_CPU_BASE_ADDR_REMAP_LOW                   0xd70
#define PCI_1_CPU_BASE_ADDR_REMAP_LOW                   0xdf0
#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH                  0xd74
#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH                  0xdf4
#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP           0xf00
#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP           0xf80
#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP             0xf38
#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP             0xfb8
#define PCI_0_ADDR_DECODE_CONTROL                       0xd3c
#define PCI_1_ADDR_DECODE_CONTROL                       0xdbc
#define PCI_0_HEADERS_RETARGET_CONTROL                  0xF40
#define PCI_1_HEADERS_RETARGET_CONTROL                  0xFc0
#define PCI_0_HEADERS_RETARGET_BASE                     0xF44
#define PCI_1_HEADERS_RETARGET_BASE                     0xFc4
#define PCI_0_HEADERS_RETARGET_HIGH                     0xF48
#define PCI_1_HEADERS_RETARGET_HIGH                     0xFc8

/***********************************/
/*   PCI Control Register Map      */
/***********************************/

#define PCI_0_DLL_STATUS_AND_COMMAND                    0x1d20
#define PCI_1_DLL_STATUS_AND_COMMAND                    0x1da0
#define PCI_0_MPP_PADS_DRIVE_CONTROL                    0x1d1C
#define PCI_1_MPP_PADS_DRIVE_CONTROL                    0x1d9C
#define PCI_0_COMMAND					0xc00
#define PCI_1_COMMAND					0xc80
#define PCI_0_MODE                                      0xd00
#define PCI_1_MODE                                      0xd80
#define PCI_0_RETRY	        			0xc04
#define PCI_1_RETRY				       	0xc84
#define PCI_0_READ_BUFFER_DISCARD_TIMER                 0xd04
#define PCI_1_READ_BUFFER_DISCARD_TIMER                 0xd84
#define PCI_0_MSI_TRIGGER_TIMER                         0xc38
#define PCI_1_MSI_TRIGGER_TIMER                         0xcb8
#define PCI_0_ARBITER_CONTROL                           0x1d00
#define PCI_1_ARBITER_CONTROL                           0x1d80
#define PCI_0_CROSS_BAR_CONTROL_LOW                     0x1d08
#define PCI_1_CROSS_BAR_CONTROL_LOW                     0x1d88
#define PCI_0_CROSS_BAR_CONTROL_HIGH                    0x1d0c
#define PCI_1_CROSS_BAR_CONTROL_HIGH                    0x1d8c
#define PCI_0_CROSS_BAR_TIMEOUT                         0x1d04
#define PCI_1_CROSS_BAR_TIMEOUT                         0x1d84
#define PCI_0_SYNC_BARRIER_TRIGGER_REG                  0x1D18
#define PCI_1_SYNC_BARRIER_TRIGGER_REG                  0x1D98
#define PCI_0_SYNC_BARRIER_VIRTUAL_REG                  0x1d10
#define PCI_1_SYNC_BARRIER_VIRTUAL_REG                  0x1d90
#define PCI_0_P2P_CONFIG                                0x1d14
#define PCI_1_P2P_CONFIG                                0x1d94

#define PCI_0_ACCESS_CONTROL_BASE_0_LOW                 0x1e00
#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH                0x1e04
#define PCI_0_ACCESS_CONTROL_SIZE_0                     0x1e08
#define PCI_0_ACCESS_CONTROL_BASE_1_LOW                 0x1e10
#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH                0x1e14
#define PCI_0_ACCESS_CONTROL_SIZE_1                     0x1e18
#define PCI_0_ACCESS_CONTROL_BASE_2_LOW                 0x1e20
#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH                0x1e24
#define PCI_0_ACCESS_CONTROL_SIZE_2                     0x1e28
#define PCI_0_ACCESS_CONTROL_BASE_3_LOW                 0x1e30
#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH                0x1e34
#define PCI_0_ACCESS_CONTROL_SIZE_3                     0x1e38
#define PCI_0_ACCESS_CONTROL_BASE_4_LOW                 0x1e40
#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH                0x1e44
#define PCI_0_ACCESS_CONTROL_SIZE_4                     0x1e48
#define PCI_0_ACCESS_CONTROL_BASE_5_LOW                 0x1e50
#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH                0x1e54
#define PCI_0_ACCESS_CONTROL_SIZE_5                     0x1e58

#define PCI_1_ACCESS_CONTROL_BASE_0_LOW                 0x1e80
#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH                0x1e84
#define PCI_1_ACCESS_CONTROL_SIZE_0                     0x1e88
#define PCI_1_ACCESS_CONTROL_BASE_1_LOW                 0x1e90
#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH                0x1e94
#define PCI_1_ACCESS_CONTROL_SIZE_1                     0x1e98
#define PCI_1_ACCESS_CONTROL_BASE_2_LOW                 0x1ea0
#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH                0x1ea4
#define PCI_1_ACCESS_CONTROL_SIZE_2                     0x1ea8
#define PCI_1_ACCESS_CONTROL_BASE_3_LOW                 0x1eb0
#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH                0x1eb4
#define PCI_1_ACCESS_CONTROL_SIZE_3                     0x1eb8
#define PCI_1_ACCESS_CONTROL_BASE_4_LOW                 0x1ec0
#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH                0x1ec4
#define PCI_1_ACCESS_CONTROL_SIZE_4                     0x1ec8
#define PCI_1_ACCESS_CONTROL_BASE_5_LOW                 0x1ed0
#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH                0x1ed4
#define PCI_1_ACCESS_CONTROL_SIZE_5                     0x1ed8

/****************************************/
/*   PCI Configuration Access Registers */
/****************************************/

#define PCI_0_CONFIG_ADDR 		                0xcf8
#define PCI_0_CONFIG_DATA_VIRTUAL_REG                   0xcfc
#define PCI_1_CONFIG_ADDR 		                0xc78
#define PCI_1_CONFIG_DATA_VIRTUAL_REG                   0xc7c
#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG	        0xc34
#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG	        0xcb4

/****************************************/
/*   PCI Error Report Registers         */
/****************************************/

#define PCI_0_SERR_MASK					0xc28
#define PCI_1_SERR_MASK					0xca8
#define PCI_0_ERROR_ADDR_LOW                            0x1d40
#define PCI_1_ERROR_ADDR_LOW                            0x1dc0
#define PCI_0_ERROR_ADDR_HIGH                           0x1d44
#define PCI_1_ERROR_ADDR_HIGH                           0x1dc4
#define PCI_0_ERROR_ATTRIBUTE                           0x1d48
#define PCI_1_ERROR_ATTRIBUTE                           0x1dc8
#define PCI_0_ERROR_COMMAND                             0x1d50
#define PCI_1_ERROR_COMMAND                             0x1dd0
#define PCI_0_ERROR_CAUSE                               0x1d58
#define PCI_1_ERROR_CAUSE                               0x1dd8
#define PCI_0_ERROR_MASK                                0x1d5c
#define PCI_1_ERROR_MASK                                0x1ddc

/****************************************/
/*   PCI Debug Registers                */
/****************************************/

#define PCI_0_MMASK                                     0X1D24
#define PCI_1_MMASK                                     0X1DA4

/*********************************************/
/* PCI Configuration, Function 0, Registers  */
/*********************************************/

#define PCI_DEVICE_AND_VENDOR_ID 			0x000