mv64460reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/* $Id: mv64460reg.h,v 1.1 2003/08/30 15:02:09 pefo Exp $ */

/*
 * Copyright (c) 2003 Opsycon AB
 * Copyright (c) 2002 Galileo Technology.
 * Copyright (c) 2002 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _MV64460REG_H_
#define _MV64460REG_H_

#include <machine/asm.h>

#ifndef _LOCORE
#include <machine/pio.h>

#define GT_WRITE(offs, data) \
	out32rb(GT_BASE_ADDR+(offs), data)

#define GT_READ(offs) \
	in32rb(GT_BASE_ADDR+(offs))
#endif

/* Always move internal space up! */
#define	GT_BASE_ADDR			0xf1000000
#define	GT_BASE_ADDR_DEFAULT		0x14000000 


#if 0
/* Supported by the Atlantis */
#define INCLUDE_PCI_1
#define INCLUDE_PCI_0_ARBITER
#define INCLUDE_PCI_1_ARBITER
#define INCLUDE_SNOOP_SUPPORT
#define INCLUDE_P2P
#define INCLUDE_ETH_PORT_2
#define INCLUDE_CPU_MAPPING 
#define INCLUDE_MPSC

/* Not supported features */ 
#undef  INCLUDE_CNTMR_4_7
#undef  INCLUDE_DMA_4_7
#endif

#define	GT_IPCI_CFGADDR_ConfigEn	(1<<31)

/* Aliases */

#define GT_BOOT_PAR 		DEVICE_BOOT_BANK_PARAMETERS

/****************************************/
/* Processor Address Space              */
/****************************************/

/* DDR SDRAM BAR and size registers */

#define CS_0_BASE_ADDR                                      0x008
#define CS_0_SIZE                                           0x010
#define CS_1_BASE_ADDR                                      0x208
#define CS_1_SIZE                                           0x210
#define CS_2_BASE_ADDR                                      0x018
#define CS_2_SIZE                                           0x020
#define CS_3_BASE_ADDR                                      0x218
#define CS_3_SIZE                                           0x220

/* Devices BAR and size registers */

#define DEV_CS0_BASE_ADDR                                   0x028
#define DEV_CS0_SIZE                                        0x030
#define DEV_CS1_BASE_ADDR                                   0x228
#define DEV_CS1_SIZE                                        0x230
#define DEV_CS2_BASE_ADDR                                   0x248
#define DEV_CS2_SIZE                                        0x250
#define DEV_CS3_BASE_ADDR                                   0x038
#define DEV_CS3_SIZE                                        0x040
#define BOOTCS_BASE_ADDR                                    0x238
#define BOOTCS_SIZE                                         0x240

/* PCI 0 BAR and size registers */

#define PCI_0_IO_BASE_ADDR                                  0x048
#define PCI_0_IO_SIZE                                       0x050
#define PCI_0_MEMORY0_BASE_ADDR                             0x058
#define PCI_0_MEMORY0_SIZE                                  0x060
#define PCI_0_MEMORY1_BASE_ADDR                             0x080
#define PCI_0_MEMORY1_SIZE                                  0x088
#define PCI_0_MEMORY2_BASE_ADDR                             0x258
#define PCI_0_MEMORY2_SIZE                                  0x260
#define PCI_0_MEMORY3_BASE_ADDR                             0x280
#define PCI_0_MEMORY3_SIZE                                  0x288

/* PCI 1 BAR and size registers */
#define PCI_1_IO_BASE_ADDR                                  0x090
#define PCI_1_IO_SIZE                                       0x098
#define PCI_1_MEMORY0_BASE_ADDR                             0x0a0
#define PCI_1_MEMORY0_SIZE                                  0x0a8
#define PCI_1_MEMORY1_BASE_ADDR                             0x0b0
#define PCI_1_MEMORY1_SIZE                                  0x0b8
#define PCI_1_MEMORY2_BASE_ADDR                             0x2a0
#define PCI_1_MEMORY2_SIZE                                  0x2a8
#define PCI_1_MEMORY3_BASE_ADDR                             0x2b0
#define PCI_1_MEMORY3_SIZE                                  0x2b8

/* SRAM base address */
#define INTEGRATED_SRAM_BASE_ADDR                           0x268

/* internal registers space base address */
#define INTERNAL_SPACE_BASE_ADDR                            0x068

/* Enables the CS , DEV_CS , PCI 0 and PCI 1 
   windows above */
#define BASE_ADDR_ENABLE                                    0x278

/****************************************/
/* PCI remap registers                  */
/****************************************/
      /* PCI 0 */
#define PCI_0_IO_ADDR_REMAP                                 0x0f0
#define PCI_0_MEMORY0_LOW_ADDR_REMAP                        0x0f8
#define PCI_0_MEMORY0_HIGH_ADDR_REMAP                       0x320
#define PCI_0_MEMORY1_LOW_ADDR_REMAP                        0x100
#define PCI_0_MEMORY1_HIGH_ADDR_REMAP                       0x328
#define PCI_0_MEMORY2_LOW_ADDR_REMAP                        0x2f8
#define PCI_0_MEMORY2_HIGH_ADDR_REMAP                       0x330
#define PCI_0_MEMORY3_LOW_ADDR_REMAP                        0x300
#define PCI_0_MEMORY3_HIGH_ADDR_REMAP                       0x338
      /* PCI 1 */
#define PCI_1_IO_ADDR_REMAP                                 0x108
#define PCI_1_MEMORY0_LOW_ADDR_REMAP                        0x110
#define PCI_1_MEMORY0_HIGH_ADDR_REMAP                       0x340
#define PCI_1_MEMORY1_LOW_ADDR_REMAP                        0x118
#define PCI_1_MEMORY1_HIGH_ADDR_REMAP                       0x348
#define PCI_1_MEMORY2_LOW_ADDR_REMAP                        0x310
#define PCI_1_MEMORY2_HIGH_ADDR_REMAP                       0x350
#define PCI_1_MEMORY3_LOW_ADDR_REMAP                        0x318
#define PCI_1_MEMORY3_HIGH_ADDR_REMAP                       0x358
 
#define CPU_PCI_0_HEADERS_RETARGET_CONTROL                  0x3b0
#define CPU_PCI_0_HEADERS_RETARGET_BASE                     0x3b8
#define CPU_PCI_1_HEADERS_RETARGET_CONTROL                  0x3c0
#define CPU_PCI_1_HEADERS_RETARGET_BASE                     0x3c8
#define CPU_GE_HEADERS_RETARGET_CONTROL                     0x3d0
#define CPU_GE_HEADERS_RETARGET_BASE                        0x3d8
#define CPU_IDMA_HEADERS_RETARGET_CONTROL                   0x3e0
#define CPU_IDMA_HEADERS_RETARGET_BASE                      0x3e8

/****************************************/
/*         CPU Control Registers        */
/****************************************/

#define CPU_CONFIG                                          0x000
#define CPU_MODE                                            0x120
#define CPU_MASTER_CONTROL                                  0x160
#define CPU_CROSS_BAR_CONTROL_LOW                           0x150
#define CPU_CROSS_BAR_CONTROL_HIGH                          0x158
#define CPU_CROSS_BAR_TIMEOUT                               0x168

/****************************************/
/* SMP RegisterS                        */
/****************************************/

#define SMP_WHO_AM_I                                        0x200
#define SMP_CPU0_DOORBELL                                   0x214
#define SMP_CPU0_DOORBELL_CLEAR                             0x21C
#define SMP_CPU1_DOORBELL                                   0x224
#define SMP_CPU1_DOORBELL_CLEAR                             0x22C
#define SMP_CPU0_DOORBELL_MASK                              0x234
#define SMP_CPU1_DOORBELL_MASK                              0x23C
#define SMP_SEMAPHOR0                                       0x244
#define SMP_SEMAPHOR1                                       0x24c
#define SMP_SEMAPHOR2                                       0x254
#define SMP_SEMAPHOR3                                       0x25c
#define SMP_SEMAPHOR4                                       0x264
#define SMP_SEMAPHOR5                                       0x26c
#define SMP_SEMAPHOR6                                       0x274
#define SMP_SEMAPHOR7                                       0x27c

/****************************************/
/*  CPU Sync Barrier Register           */
/****************************************/

#define CPU_0_SYNC_BARRIER_TRIGGER                          0x0c0
#define CPU_0_SYNC_BARRIER_VIRTUAL                          0x0c8
#define CPU_1_SYNC_BARRIER_TRIGGER                          0x0d0
#define CPU_1_SYNC_BARRIER_VIRTUAL                          0x0d8

/****************************************/
/* CPU Access Protect                   */
/****************************************/

#define CPU_PROTECT_WINDOW_0_BASE_ADDR                      0x180
#define CPU_PROTECT_WINDOW_0_SIZE                           0x188
#define CPU_PROTECT_WINDOW_1_BASE_ADDR                      0x190
#define CPU_PROTECT_WINDOW_1_SIZE                           0x198
#define CPU_PROTECT_WINDOW_2_BASE_ADDR                      0x1a0
#define CPU_PROTECT_WINDOW_2_SIZE                           0x1a8
#define CPU_PROTECT_WINDOW_3_BASE_ADDR                      0x1b0
#define CPU_PROTECT_WINDOW_3_SIZE                           0x1b8


/****************************************/
/*          CPU Error Report            */
/****************************************/

#define CPU_ERROR_ADDR_LOW                                  0x070
#define CPU_ERROR_ADDR_HIGH                                 0x078
#define CPU_ERROR_DATA_LOW                                  0x128
#define CPU_ERROR_DATA_HIGH                                 0x130
#define CPU_ERROR_PARITY                                    0x138
#define CPU_ERROR_CAUSE                                     0x140
#define CPU_ERROR_MASK                                      0x148

/****************************************/
/*      CPU Interface Debug Registers 	*/
/****************************************/

#define PUNIT_SLAVE_DEBUG_LOW                               0x360
#define PUNIT_SLAVE_DEBUG_HIGH                              0x368
#define PUNIT_MASTER_DEBUG_LOW                              0x370
#define PUNIT_MASTER_DEBUG_HIGH                             0x378
#define PUNIT_MMASK                                         0x3e4

/****************************************/
/*  Integrated SRAM Registers           */
/****************************************/

#define SRAM_CONFIG                                         0x380
#define SRAM_TEST_MODE                                      0X3F4
#define SRAM_ERROR_CAUSE                                    0x388
#define SRAM_ERROR_ADDR                                     0x390
#define SRAM_ERROR_ADDR_HIGH                                0X3F8
#define SRAM_ERROR_DATA_LOW                                 0x398
#define SRAM_ERROR_DATA_HIGH                                0x3a0
#define SRAM_ERROR_DATA_PARITY                              0x3a8

/****************************************/
/* SDRAM Configuration                  */
/****************************************/

#define SDRAM_CONFIG                                        0x1400
#define D_UNIT_CONTROL_LOW                                  0x1404
#define D_UNIT_CONTROL_HIGH                                 0x1424
#define SDRAM_TIMING_CONTROL_LOW                            0x1408
#define SDRAM_TIMING_CONTROL_HIGH                           0x140c
#define SDRAM_ADDR_CONTROL                                  0x1410
#define SDRAM_OPEN_PAGES_CONTROL                            0x1414
#define SDRAM_OPERATION                                     0x1418
#define SDRAM_MODE                                          0x141c