mv64440reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)            (0x2700 + (port<<10))
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)            (0x2710 + (port<<10))
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)            (0x2720 + (port<<10))
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)            (0x2730 + (port<<10))
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)            (0x2740 + (port<<10))
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)            (0x2750 + (port<<10))
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)            (0x2760 + (port<<10))
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)            (0x2770 + (port<<10))
#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)           (0x2704 + (port<<10))
#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)           (0x2714 + (port<<10))
#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)           (0x2724 + (port<<10))
#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)           (0x2734 + (port<<10))
#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)           (0x2744 + (port<<10))
#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)           (0x2754 + (port<<10))
#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)           (0x2764 + (port<<10))
#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)           (0x2774 + (port<<10))
#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)                (0x2708 + (port<<10))
#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)                (0x2718 + (port<<10))
#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)                (0x2728 + (port<<10))
#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)                (0x2738 + (port<<10))
#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)                (0x2748 + (port<<10))
#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)                (0x2758 + (port<<10))
#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)                (0x2768 + (port<<10))
#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)                (0x2778 + (port<<10))
#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)               (0x2780 + (port<<10))
#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)     (0x3500 + (port<<10))
#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)             (0x3600 + (port<<10))

/****************************************/
/* Communication Unit Registers         */
/****************************************/

#define ETHERNET_0_ADDRESS_CONTROL_LOW			    0xf200
#define ETHERNET_0_ADDRESS_CONTROL_HIGH                     0xf204
#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf208
#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf20c
#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf210
#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf214
#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS              0xf218
#define ETHERNET_1_ADDRESS_CONTROL_LOW                      0xf220
#define ETHERNET_1_ADDRESS_CONTROL_HIGH                     0xf224
#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf228
#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf22c
#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf230
#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf234
#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS              0xf238
#define ETHERNET_2_ADDRESS_CONTROL_LOW                      0xf240
#define ETHERNET_2_ADDRESS_CONTROL_HIGH                     0xf244
#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf248
#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf24c
#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf250
#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf254
#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS              0xf258
#define MPSC_0_ADDRESS_CONTROL_LOW                          0xf280
#define MPSC_0_ADDRESS_CONTROL_HIGH                         0xf284
#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf288
#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf28c
#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf290
#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf294
#define MPSC_1_ADDRESS_CONTROL_LOW                          0xf2a0
#define MPSC_1_ADDRESS_CONTROL_HIGH                         0xf2a4
#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf2a8
#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf2ac
#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf2b0
#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf2b4
#define MPSC_2_ADDRESS_CONTROL_LOW                          0xf2c0
#define MPSC_2_ADDRESS_CONTROL_HIGH                         0xf2c4
#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf2c8
#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf2cc
#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf2d0
#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf2d4
#define SERIAL_INIT_PCI_HIGH_ADDRESS                        0xf320
#define SERIAL_INIT_LAST_DATA                               0xf324
#define SERIAL_INIT_STATUS_AND_CONTROL                      0xf328
#define COMM_UNIT_ARBITER_CONTROL                           0xf300
#define COMM_UNIT_CROSS_BAR_TIMEOUT                         0xf304
#define COMM_UNIT_INTERRUPT_CAUSE                           0xf310
#define COMM_UNIT_INTERRUPT_MASK                            0xf314
#define COMM_UNIT_ERROR_ADDRESS                             0xf314
           
/****************************************/
/* Cunit Debug  (for internal use)     */
/****************************************/

#define CUNIT_ADDRESS                                       0xf340
#define CUNIT_COMMAND_AND_ID                                0xf344
#define CUNIT_WRITE_DATA_LOW                                0xf348
#define CUNIT_WRITE_DATA_HIGH                               0xf34c
#define CUNIT_WRITE_BYTE_ENABLE                             0xf358
#define CUNIT_READ_DATA_LOW                                 0xf350
#define CUNIT_READ_DATA_HIGH                                0xf354
#define CUNIT_READ_ID                                       0xf35c

/****************************************/
/* SDMA Registers                       */
/****************************************/

#define SDMA_GROUP_CONFIGURATION_REGISTER                   0xb1f0
#define CHANNEL0_CONFIGURATION_REGISTER                     0x4000
#define CHANNEL0_COMMAND_REGISTER                           0x4008
#define CHANNEL0_RX_CMD_STATUS                              0x4800
#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES                 0x4804
#define CHANNEL0_RX_BUFFER_POINTER                          0x4808
#define CHANNEL0_RX_NEXT_POINTER                            0x480c
#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER              0x4810
#define CHANNEL0_TX_CMD_STATUS                              0x4C00
#define CHANNEL0_TX_PACKET_SIZE                             0x4C04
#define CHANNEL0_TX_BUFFER_POINTER                          0x4C08
#define CHANNEL0_TX_NEXT_POINTER                            0x4C0c
#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER              0x4c10
#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER                0x4c14
#define CHANNEL1_CONFIGURATION_REGISTER                     0x5000
#define CHANNEL1_COMMAND_REGISTER                           0x5008
#define CHANNEL1_RX_CMD_STATUS                              0x5800
#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES                 0x5804
#define CHANNEL1_RX_BUFFER_POINTER                          0x5808
#define CHANNEL1_RX_NEXT_POINTER                            0x580c
#define CHANNEL1_TX_CMD_STATUS                              0x5C00
#define CHANNEL1_TX_PACKET_SIZE                             0x5C04
#define CHANNEL1_TX_BUFFER_POINTER                          0x5C08
#define CHANNEL1_TX_NEXT_POINTER                            0x5C0c
#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER              0x5810
#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER              0x5c10
#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER                0x5c14
#define CHANNEL2_CONFIGURATION_REGISTER                     0x6000
#define CHANNEL2_COMMAND_REGISTER                           0x6008
#define CHANNEL2_RX_CMD_STATUS                              0x6800
#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES                 0x6804
#define CHANNEL2_RX_BUFFER_POINTER                          0x6808
#define CHANNEL2_RX_NEXT_POINTER                            0x680c
#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER              0x6810
#define CHANNEL2_TX_CMD_STATUS                              0x6C00
#define CHANNEL2_TX_PACKET_SIZE                             0x6C04
#define CHANNEL2_TX_BUFFER_POINTER                          0x6C08
#define CHANNEL2_TX_NEXT_POINTER                            0x6C0c
#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER              0x6810
#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER              0x6c10
#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER                0x6c14

/* SDMA Interrupt */

#define SDMA_CAUSE                                          0xb820
#define SDMA_MASK                                           0xb8a0


/****************************************/
/* Baude Rate Generators Registers      */
/****************************************/

/* BRG 0 */

#define BRG0_CFG_REG                         		    0xb200
#define BRG0_BAUD_TUNING_REG                                0xb204

/* BRG 1 */

#define BRG1_CFG_REG                                        0xb208
#define BRG1_BAUD_TUNING_REG                                0xb20c

/* BRG 2 */

#define BRG2_CFG_REGISTER                                   0xb210
#define BRG2_BAUD_TUNING_REG                                0xb214

/* BRG Interrupts */

#define BRG_CAUSE_REGISTER                                  0xb834
#define BRG_MASK_REGISTER                                   0xb8b4

/* MISC */

#define MAIN_ROUTING_REGISTER                               0xb400
#define RECEIVE_CLOCK_ROUTING_REGISTER                      0xb404
#define TRANSMIT_CLOCK_ROUTING_REGISTER                     0xb408
#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER            0xb40c
#define WATCHDOG_CONFIGURATION_REGISTER                     0xb410
#define WATCHDOG_VALUE_REGISTER                             0xb410


/****************************************/
/* Flex TDM Registers                   */
/****************************************/

/* FTDM Port */

#define FLEXTDM_TRANSMIT_READ_POINTER                       0xa800
#define FLEXTDM_RECEIVE_READ_POINTER                        0xa804
#define FLEXTDM_CONFIGURATION_REGISTER                      0xa808
#define FLEXTDM_AUX_CHANNELA_TX_REGISTER                    0xa80c
#define FLEXTDM_AUX_CHANNELA_RX_REGISTER                    0xa810
#define FLEXTDM_AUX_CHANNELB_TX_REGISTER                    0xa814
#define FLEXTDM_AUX_CHANNELB_RX_REGISTER                    0xa818

/* FTDM Interrupts */

#define FTDM_CAUSE_REGISTER                                 0xb830
#define FTDM_MASK_REGISTER                                  0xb8b0


/****************************************/
/* GPP Interface Registers              */
/****************************************/

/* MDD This section done */

#define GPP_IO_CONTROL                                      0xf100
#define GPP_LEVEL_CONTROL                                   0xf110
#define GPP_VALUE                                           0xf104
#define GPP_INTERRUPT_CAUSE                                 0xf108
#define GPP_INTERRUPT_MASK                                  0xf10c

#define MPP_CONTROL0                                        0xf000
#define MPP_CONTROL1                                        0xf004
#define MPP_CONTROL2                                        0xf008
#define MPP_CONTROL3                                        0xf00c

/****************************************/
/* I2C Registers                        */
/****************************************/

#define I2C_SLAVE_ADDRESS                                   0xc000
#define I2C_EXTENDED_SLAVE_ADDRESS                          0xc040
#define I2C_DATA                                            0xc004
#define I2C_CONTROL                                         0xc008
#define I2C_STATUS_BAUDE_RATE                               0xc00C
#define I2C_SOFT_RESET                                      0xc01c

/****************************************/ 
/* MPSC Registers                       */ 
/****************************************/ 

/* MPSC0  */

#define MPSC0_MAIN_CONFIGURATION_LOW                        0x8000
#define MPSC0_MAIN_CONFIGURATION_HIGH                       0x8004
#define MPSC0_PROTOCOL_CONFIGURATION                        0x8008
#define CHANNEL0_REGISTER1                                  0x800c
#define CHANNEL0_REGISTER2                                  0x8010 
#define CHANNEL0_REGISTER3                                  0x8014 
#define CHANNEL0_REGISTER4                                  0x8018 
#define CHANNEL0_REGISTER5                                  0x801c 
#define CHANNEL0_REGISTER6                                  0x8020 
#define CHANNEL0_REGISTER7                                  0x8024 
#define CHANNEL0_REGISTER8                                  0x8028 
#define CHANNEL0_REGISTER9                                  0x802c 
#define CHANNEL0_REGISTER10                                 0x8030 
#define CHANNEL0_REGISTER11                                 0x8034

/* MPSC1  */

#define MPSC1_MAIN_CONFIGURATION_LOW                        0x8840
#define MPSC1_MAIN_CONFIGURATION_HIGH                       0x8844
#define MPSC1_PROTOCOL_CONFIGURATION                        0x8848
#define CHANNEL1_REGISTER1                                  0x884c
#define CHANNEL1_REGISTER2                                  0x8850 
#define CHANNEL1_REGISTER3                                  0x8854 
#define CHANNEL1_REGISTER4                                  0x8858 
#define CHANNEL1_REGISTER5                                  0x885c 
#define CHANNEL1_REGISTER6                                  0x8860 
#define CHANNEL1_REGISTER7                                  0x8864 
#define CHANNEL1_REGISTER8                                  0x8868 
#define CHANNEL1_REGISTER9                                  0x886c 
#define CHANNEL1_REGISTER10                                 0x8870 
#define CHANNEL1_REGISTER11                                 0x8874
      
/* MPSC2  */

#define MPSC2_MAIN_CONFIGURATION_LOW                        0x9040
#define MPSC2_MAIN_CONFIGURATION_HIGH                       0x9044
#define MPSC2_PROTOCOL_CONFIGURATION                        0x9048
#define CHANNEL2_REGISTER1                                  0x904c
#define CHANNEL2_REGISTER2                                  0x9050 
#define CHANNEL2_REGISTER3                                  0x9054 
#define CHANNEL2_REGISTER4                                  0x9058 
#define CHANNEL2_REGISTER5                                  0x905c 
#define CHANNEL2_REGISTER6                                  0x9060 
#define CHANNEL2_REGISTER7                                  0x9064 
#define CHANNEL2_REGISTER8                                  0x9068 
#define CHANNEL2_REGISTER9                                  0x906c 
#define CHANNEL2_REGISTER10                                 0x9070 
#define CHANNEL2_REGISTER11                                 0x9074

/* MPSCs Interupts  */

#define MPSC0_CAUSE                                         0xb824
#define MPSC0_MASK                                          0xb8a4
#define MPSC1_CAUSE                                         0xb828
#define MPSC1_MASK                                          0xb8a8
#define MPSC2_CAUSE                                         0xb82c
#define MPSC2_MASK                                          0xb8ac

#endif /* _MV64440REG_H_ */