mv64440reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#define PCI_1ACCESS_CONTROL_TOP_1                            0x1e98
#define PCI_1ACCESS_CONTROL_BASE_2_LOW                       0c1ea0
#define PCI_1ACCESS_CONTROL_BASE_2_HIGH                      0x1ea4
#define PCI_1ACCESS_CONTROL_TOP_2                            0x1ea8
#define PCI_1ACCESS_CONTROL_BASE_3_LOW                       0c1eb0
#define PCI_1ACCESS_CONTROL_BASE_3_HIGH                      0x1eb4
#define PCI_1ACCESS_CONTROL_TOP_3                            0x1eb8
#define PCI_1ACCESS_CONTROL_BASE_4_LOW                       0c1ec0
#define PCI_1ACCESS_CONTROL_BASE_4_HIGH                      0x1ec4
#define PCI_1ACCESS_CONTROL_TOP_4                            0x1ec8
#define PCI_1ACCESS_CONTROL_BASE_5_LOW                       0c1ed0
#define PCI_1ACCESS_CONTROL_BASE_5_HIGH                      0x1ed4
#define PCI_1ACCESS_CONTROL_TOP_5                            0x1ed8
#define PCI_1ACCESS_CONTROL_BASE_6_LOW                       0c1ee0
#define PCI_1ACCESS_CONTROL_BASE_6_HIGH                      0x1ee4
#define PCI_1ACCESS_CONTROL_TOP_6                            0x1ee8
#define PCI_1ACCESS_CONTROL_BASE_7_LOW                       0c1ef0
#define PCI_1ACCESS_CONTROL_BASE_7_HIGH                      0x1ef4
#define PCI_1ACCESS_CONTROL_TOP_7                            0x1ef8

/****************************************/
/* PCI Configuration Address            */
/****************************************/

/* MDD This section done */

#define PCI_0CONFIGURATION_ADDRESS 				0xcf8
#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xcfc
#define PCI_1CONFIGURATION_ADDRESS 				0xc78
#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xc7c
#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xc34
#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xcb4

/****************************************/
/* PCI Error Report                     */
/****************************************/

/* MDD This section done */

#define PCI_0SERR_MASK						0xc28
#define PCI_0ERROR_ADDRESS_LOW					0x1d40
#define PCI_0ERROR_ADDRESS_HIGH					0x1d44
#define PCI_0ERROR_ATTRIBUTE					0x1d48
#define PCI_0ERROR_COMMAND					0x1d50
#define PCI_0ERROR_CAUSE					0x1d58
#define PCI_0ERROR_MASK						0x1d5c

#define PCI_1SERR_MASK						0xca8
#define PCI_1ERROR_ADDRESS_LOW					0x1dc0
#define PCI_1ERROR_ADDRESS_HIGH					0x1dc4
#define PCI_1ERROR_ATTRIBUTE					0x1dc8
#define PCI_1ERROR_COMMAND					0x1dd0
#define PCI_1ERROR_CAUSE					0x1dd8
#define PCI_1ERROR_MASK						0x1ddc

/****************************************/
/* PCI Configuration Function 0         */
/****************************************/

/* MDD This section done */

#define PCI_DEVICE_AND_VENDOR_ID 				0x000
#define PCI_STATUS_AND_COMMAND					0x004
#define PCI0_COMMAND_STATUS_REG        				0x004
#define PCI1_COMMAND_STATUS_REG        				0x084
#define PCI_CLASS_CODE_AND_REVISION_ID			        0x008
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 		0x00C
#define PCI_SCS_0_BASE_ADDRESS_LOW    				0x010
#define PCI_SCS_0_BASE_ADDRESS_HIGH			    	0x014
#define PCI_SCS_1_BASE_ADDRESS_LOW				0x018
#define PCI_SCS_1_BASE_ADDRESS_HIGH   				0x01C
#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID		0x02C
#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER			0x030
#define PCI_CAPABILTY_LIST_POINTER                          	0x034
#define PCI_INTERRUPT_PIN_AND_LINE 			    	0x03C
#define PCI_POWER_MANAGEMENT_CAPABILITY                     0x040
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL             0x044
#define PCI_VPD_ADDRESS                                     0x048
#define PCI_VPD_DATA                                        0X04c
#define PCI_MSI_MESSAGE_CONTROL                             0x050
#define PCI_MSI_MESSAGE_ADDRESS                             0x054
#define PCI_MSI_MESSAGE_UPPER_ADDRESS                       0x058
#define PCI_MSI_MESSAGE_DATA                                0x05c
#define PCI_X_COMMAND					    0x060
#define PCI_X_STATUS					    0x064
#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY                 0x068

/****************************************/
/* PCI Configuration Function 1         */
/****************************************/

/* MDD This section done */

#define PCI_SCS_2_BASE_ADDRESS_LOW    				0x110
#define PCI_SCS_2_BASE_ADDRESS_HIGH    				0x114
#define PCI_SCS_3_BASE_ADDRESS_LOW    				0x118
#define PCI_SCS_3_BASE_ADDRESS_HIGH    				0x11c
#define PCI_INTEGRATED_SRAM_BASE_ADDRESS_LOW   			0x120
#define PCI_INTEGRATED_SRAM_BASE_ADDRESS_HIGH			0x124

/****************************************/
/* PCI Configuration Function 2         */
/****************************************/

/* MDD This section done */

#define PCI_CS_0_BASE_ADDRESS_LOW	    			0x210
#define PCI_CS_0_BASE_ADDRESS_HIGH 				0x214
#define PCI_CS_1_BASE_ADDRESS_LOW	    			0x218
#define PCI_CS_1_BASE_ADDRESS_HIGH 				0x21c
#define PCI_CS_2_BASE_ADDRESS_LOW	    			0x220
#define PCI_CS_2_BASE_ADDRESS_HIGH 				0x224

/****************************************/
/* PCI Configuration Function 3         */
/****************************************/

/* MDD This section done */

#define PCI_CS_3_BASE_ADDRESS_LOW	    			0x310
#define PCI_CS_3_BASE_ADDRESS_HIGH 				0x314
#define PCI_BOOTCS_BASE_ADDRESS_LOW	    			0x318
#define PCI_BOOTCS_BASE_ADDRESS_HIGH 				0x31c

/****************************************/
/* PCI Configuration Function 4         */
/****************************************/

/* MDD This section done */

#define PCI_P2P_MEM0_BASE_ADDRESS_LOW 				0x410
#define PCI_P2P_MEM0_BASE_ADDRESS_HIGH			    	0x414
#define PCI_P2P_MEM1_BASE_ADDRESS_LOW 				0x418
#define PCI_P2P_MEM1_BASE_ADDRESS_HIGH			    	0x41c
#define PCI_P2P_I_O_BASE_ADDRESS 				0x420
#define PCI_INTERNAL_REGS_ADDRESS_BASE			    	0x424

/****************************************/
/* Interrupts	  			*/
/****************************************/
			
#define LOW_INTERRUPT_CAUSE_REGISTER   				0xc18
#define HIGH_INTERRUPT_CAUSE_REGISTER				0xc68
#define CPU_INTERRUPT_MASK_REGISTER_LOW				0xc1c
#define CPU_INTERRUPT_MASK_REGISTER_HIGH			0xc6c
#define CPU_SELECT_CAUSE_REGISTER				0xc70
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xc24
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xc64
#define PCI_0SELECT_CAUSE                                   	0xc74
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xca4
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xce4
#define PCI_1SELECT_CAUSE                                   	0xcf4
#define CPU_INT_0_MASK                                      	0xe60
#define CPU_INT_1_MASK                                      	0xe64
#define CPU_INT_2_MASK                                      	0xe68
#define CPU_INT_3_MASK                                      	0xe6c

/****************************************/
/* I20 Support registers		*/
/****************************************/

#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE			0x010
#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE  			0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 			0x018
#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE  			0x01C
#define INBOUND_DOORBELL_REGISTER_PCI_SIDE  			0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE  		0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE		0x028
#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 			0x02C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE   		0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE   		0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE  		0x040
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE   	0x044
#define QUEUE_CONTROL_REGISTER_PCI_SIDE 			0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 			0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE		0x060
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE  		0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 		0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 		0x06C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE		0x070
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE		0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE		0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE		0x07C

#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE			0X1C10
#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE  			0X1C14
#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 			0X1C18
#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE  			0X1C1C
#define INBOUND_DOORBELL_REGISTER_CPU_SIDE  			0X1C20
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE  		0X1C24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE		0X1C28
#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 			0X1C2C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE   		0X1C30
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE   		0X1C34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE  		0X1C40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE   	0X1C44
#define QUEUE_CONTROL_REGISTER_CPU_SIDE 			0X1C50
#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 			0X1C54
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0X1C60
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE  		0X1C64
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 		0X1C68
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 		0X1C6C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0X1C70
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0X1C74
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0X1C78
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0X1C7C

/****************************************/
/*        Ethernet Unit Registers  		*/
/****************************************/

#define ETH_PHY_ADDR_REG                                     0x2000
#define ETH_SMI_REG                                          0x2004
#define ETH_UNIT_DEFAULT_ADDR_REG                            0x2008
#define ETH_UNIT_DEFAULTID_REG                               0x200c
#define ETH_UNIT_INTERRUPT_CAUSE_REG                         0x2080
#define ETH_UNIT_INTERRUPT_MASK_REG                          0x2084
#define ETH_UNIT_INTERNAL_USE_REG                            0x24fc
#define ETH_UNIT_ERROR_ADDR_REG                              0x2094
#define ETH_BAR_0                                            0x2200
#define ETH_BAR_1                                            0x2208
#define ETH_BAR_2                                            0x2210
#define ETH_BAR_3                                            0x2218
#define ETH_BAR_4                                            0x2220
#define ETH_BAR_5                                            0x2228
#define ETH_SIZE_REG_0                                       0x2204
#define ETH_SIZE_REG_1                                       0x220c
#define ETH_SIZE_REG_2                                       0x2214
#define ETH_SIZE_REG_3                                       0x221c
#define ETH_SIZE_REG_4                                       0x2224
#define ETH_SIZE_REG_5                                       0x222c
#define ETH_HEADERS_RETARGET_BASE_REG                        0x2230
#define ETH_HEADERS_RETARGET_CONTROL_REG                     0x2234
#define ETH_HIGH_ADDR_REMAP_REG_0                            0x2280
#define ETH_HIGH_ADDR_REMAP_REG_1                            0x2284
#define ETH_HIGH_ADDR_REMAP_REG_2                            0x2288
#define ETH_HIGH_ADDR_REMAP_REG_3                            0x228c
#define ETH_BASE_ADDR_ENABLE_REG                             0x2290
#define ETH_ACCESS_PROTECTION_REG(port)                    (0x2294 + (port<<2))
#define ETH_MIB_COUNTERS_BASE(port)                        (0x3000 + (port<<7))
#define ETH_PORT_CONFIG_REG(port)                          (0x2400 + (port<<10))
#define ETH_PORT_CONFIG_EXTEND_REG(port)                   (0x2404 + (port<<10))
#define ETH_MII_SERIAL_PARAMETRS_REG(port)                 (0x2408 + (port<<10))
#define ETH_GMII_SERIAL_PARAMETRS_REG(port)                (0x240c + (port<<10))
#define ETH_VLAN_ETHERTYPE_REG(port)                       (0x2410 + (port<<10))
#define ETH_MAC_ADDR_LOW(port)                             (0x2414 + (port<<10))
#define ETH_MAC_ADDR_HIGH(port)                            (0x2418 + (port<<10))
#define ETH_SDMA_CONFIG_REG(port)                          (0x241c + (port<<10))
#define ETH_DSCP_0(port)                                   (0x2420 + (port<<10))
#define ETH_DSCP_1(port)                                   (0x2424 + (port<<10))
#define ETH_DSCP_2(port)                                   (0x2428 + (port<<10))
#define ETH_DSCP_3(port)                                   (0x242c + (port<<10))
#define ETH_DSCP_4(port)                                   (0x2430 + (port<<10))
#define ETH_DSCP_5(port)                                   (0x2434 + (port<<10))
#define ETH_DSCP_6(port)                                   (0x2438 + (port<<10))
#define ETH_PORT_SERIAL_CONTROL_REG(port)                  (0x243c + (port<<10))
#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)            (0x2440 + (port<<10))
#define ETH_PORT_STATUS_REG(port)                          (0x2444 + (port<<10))
#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)               (0x2448 + (port<<10))
#define ETH_TX_QUEUE_FIXED_PRIORITY(port)                  (0x244c + (port<<10))
#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)         (0x2450 + (port<<10))
#define ETH_MAXIMUM_TRANSMIT_UNIT(port)                    (0x2458 + (port<<10))
#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)           (0x245c + (port<<10))
#define ETH_INTERRUPT_CAUSE_REG(port)                      (0x2460 + (port<<10))
#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)               (0x2464 + (port<<10))
#define ETH_INTERRUPT_MASK_REG(port)                       (0x2468 + (port<<10))
#define ETH_INTERRUPT_EXTEND_MASK_REG(port)                (0x246c + (port<<10))
#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)             (0x2470 + (port<<10))
#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)             (0x2474 + (port<<10))
#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)                (0x247c + (port<<10))
#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)              (0x2484 + (port<<10))
#define ETH_PORT_DEBUG_0_REG(port)                         (0x248c + (port<<10))
#define ETH_PORT_DEBUG_1_REG(port)                         (0x2490 + (port<<10))
#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)             (0x2494 + (port<<10))
#define ETH_INTERNAL_USE_REG(port)                         (0x24fc + (port<<10))
#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)                (0x2680 + (port<<10))
#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)               (0x2684 + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)              (0x260c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)              (0x261c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)              (0x262c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)              (0x263c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)              (0x264c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)              (0x265c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)              (0x266c + (port<<10))
#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)              (0x267c + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)              (0x26c0 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)              (0x26c4 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)              (0x26c8 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)              (0x26cc + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)              (0x26d0 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)              (0x26d4 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)              (0x26d8 + (port<<10))
#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)              (0x26dc + (port<<10))