gt64240reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#define L_SLAVE_X0_COMMAND_AND_ID                           0x1d24
#define L_SLAVE_X1_ADDRESS                                  0x1d28
#define L_SLAVE_X1_COMMAND_AND_ID                           0x1d2c
#define L_SLAVE_WRITE_DATA_LOW                              0x1d30
#define L_SLAVE_WRITE_DATA_HIGH                             0x1d34
#define L_SLAVE_WRITE_BYTE_ENABLE                           0x1d60
#define L_SLAVE_READ_DATA_LOW                               0x1d38
#define L_SLAVE_READ_DATA_HIGH                              0x1d3c
#define L_SLAVE_READ_ID                                     0x1d64

/****************************************/
/* PCI Configuration Function 0         */
/****************************************/

#define PCI_DEVICE_AND_VENDOR_ID 				0x000
#define PCI_STATUS_AND_COMMAND					0x004
#define PCI0_COMMAND_STATUS_REG        				0x004
#define PCI1_COMMAND_STATUS_REG        				0x084
#define PCI_CLASS_CODE_AND_REVISION_ID			        0x008
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 		0x00C
#define PCI_SCS_0_BASE_ADDRESS	    				0x010
#define PCI_SCS_1_BASE_ADDRESS 				    	0x014
#define PCI_SCS_2_BASE_ADDRESS 					0x018
#define PCI_SCS_3_BASE_ADDRESS      				0x01C
#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID		0x02C
#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER			0x030
#define PCI_CAPABILTY_LIST_POINTER                          	0x034
#define PCI_INTERRUPT_PIN_AND_LINE 			    	0x03C
#define PCI_POWER_MANAGEMENT_CAPABILITY                     0x040
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL             0x044
#define PCI_VPD_ADDRESS                                     0x048
#define PCI_VPD_DATA                                        0X04c
#define PCI_MSI_MESSAGE_CONTROL                             0x050
#define PCI_MSI_MESSAGE_ADDRESS                             0x054
#define PCI_MSI_MESSAGE_UPPER_ADDRESS                       0x058
#define PCI_MSI_MESSAGE_DATA                                0x05c
#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY                 0x058

/****************************************/
/* PCI Configuration Function 1         */
/****************************************/

#define PCI_CS_0_BASE_ADDRESS	    				0x110
#define PCI_CS_1_BASE_ADDRESS 				    	0x114
#define PCI_CS_2_BASE_ADDRESS 					0x118
#define PCI_CS_3_BASE_ADDRESS     				0x11c
#define PCI_BOOTCS_BASE_ADDRESS                     	    	0x120

/****************************************/
/* PCI Configuration Function 2         */
/****************************************/

#define PCI_P2P_MEM0_BASE_ADDRESS	    			0x210
#define PCI_P2P_MEM1_BASE_ADDRESS 				0x214
#define PCI_P2P_I_O_BASE_ADDRESS 				0x218
#define PCI_CPU_BASE_ADDRESS      			    	0x21c

/****************************************/
/* PCI Configuration Function 4         */
/****************************************/

#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 				0x410
#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH			    	0x414
#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW   			0x418
#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH  			0x41c
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW              	    	0x420
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH             	    	0x424


/****************************************/
/* PCI Configuration Function 5         */
/****************************************/

#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 				0x510
#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH				0x514
#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW   			0x518
#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH  			0x51c
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW              	    	0x520
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH             	    	0x524


/****************************************/
/* PCI Configuration Function 6         */
/****************************************/

#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 				0x610
#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH				0x614
#define PCI_DAC_CS_1_BASE_ADDRESS_LOW   			0x618
#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH  			0x61c
#define PCI_DAC_CS_2_BASE_ADDRESS_LOW            	        0x620
#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH           	        0x624

/****************************************/
/* PCI Configuration Function 7         */
/****************************************/

#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 				0x710
#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH			    	0x714
#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW   			0x718
#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH  			0x71c
#define PCI_DAC_CPU_BASE_ADDRESS_LOW            	        0x720
#define PCI_DAC_CPU_BASE_ADDRESS_HIGH           	        0x724

/****************************************/
/* Interrupts	  			*/
/****************************************/
			
#define LOW_INTERRUPT_CAUSE_REGISTER   				0xc18
#define HIGH_INTERRUPT_CAUSE_REGISTER				0xc68
#define CPU_INTERRUPT_MASK_REGISTER_LOW				0xc1c
#define CPU_INTERRUPT_MASK_REGISTER_HIGH			0xc6c
#define CPU_SELECT_CAUSE_REGISTER				0xc70
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xc24
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xc64
#define PCI_0SELECT_CAUSE                                   	0xc74
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xca4
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xce4
#define PCI_1SELECT_CAUSE                                   	0xcf4
#define CPU_INT_0_MASK                                      	0xe60
#define CPU_INT_1_MASK                                      	0xe64
#define CPU_INT_2_MASK                                      	0xe68
#define CPU_INT_3_MASK                                      	0xe6c

/****************************************/
/* I20 Support registers		*/
/****************************************/

#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE			0x010
#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE  			0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 			0x018
#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE  			0x01C
#define INBOUND_DOORBELL_REGISTER_PCI_SIDE  			0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE  		0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE		0x028
#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 			0x02C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE   		0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE   		0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE  		0x040
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE   	0x044
#define QUEUE_CONTROL_REGISTER_PCI_SIDE 					0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 			0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE		0x060
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE  		0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 		0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 		0x06C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE		0x070
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE		0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE		0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE		0x07C

#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE			0X1C10
#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE  			0X1C14
#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 			0X1C18
#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE  			0X1C1C
#define INBOUND_DOORBELL_REGISTER_CPU_SIDE  			0X1C20
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE  		0X1C24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE		0X1C28
#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 			0X1C2C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE   		0X1C30
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE   		0X1C34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE  		0X1C40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE   	0X1C44
#define QUEUE_CONTROL_REGISTER_CPU_SIDE 			0X1C50
#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 			0X1C54
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0X1C60
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE  		0X1C64
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 		0X1C68
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 		0X1C6C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0X1C70
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0X1C74
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0X1C78
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0X1C7C

/****************************************/
/* Communication Unit Registers         */
/****************************************/

#define ETHERNET_0_ADDRESS_CONTROL_LOW				0xf200
#define ETHERNET_0_ADDRESS_CONTROL_HIGH                     0xf204
#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf208
#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf20c
#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf210
#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf214
#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS              0xf218
#define ETHERNET_1_ADDRESS_CONTROL_LOW                      0xf220
#define ETHERNET_1_ADDRESS_CONTROL_HIGH                     0xf224
#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf228
#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf22c
#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf230
#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf234
#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS              0xf238
#define ETHERNET_2_ADDRESS_CONTROL_LOW                      0xf240
#define ETHERNET_2_ADDRESS_CONTROL_HIGH                     0xf244
#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf248
#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf24c
#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf250
#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf254
#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS              0xf258
#define MPSC_0_ADDRESS_CONTROL_LOW                          0xf280
#define MPSC_0_ADDRESS_CONTROL_HIGH                         0xf284
#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf288
#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf28c
#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf290
#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf294
#define MPSC_1_ADDRESS_CONTROL_LOW                          0xf2a0
#define MPSC_1_ADDRESS_CONTROL_HIGH                         0xf2a4
#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf2a8
#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf2ac
#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf2b0
#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf2b4
#define MPSC_2_ADDRESS_CONTROL_LOW                          0xf2c0
#define MPSC_2_ADDRESS_CONTROL_HIGH                         0xf2c4
#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf2c8
#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf2cc
#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf2d0
#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf2d4
#define SERIAL_INIT_PCI_HIGH_ADDRESS                        0xf320
#define SERIAL_INIT_LAST_DATA                               0xf324
#define SERIAL_INIT_STATUS_AND_CONTROL                      0xf328
#define COMM_UNIT_ARBITER_CONTROL                           0xf300
#define COMM_UNIT_CROSS_BAR_TIMEOUT                         0xf304
#define COMM_UNIT_INTERRUPT_CAUSE                           0xf310
#define COMM_UNIT_INTERRUPT_MASK                            0xf314
#define COMM_UNIT_ERROR_ADDRESS                             0xf314
           
/****************************************/
/* Cunit Debug  (for internal use)     */
/****************************************/

#define CUNIT_ADDRESS                                       0xf340
#define CUNIT_COMMAND_AND_ID                                0xf344
#define CUNIT_WRITE_DATA_LOW                                0xf348
#define CUNIT_WRITE_DATA_HIGH                               0xf34c
#define CUNIT_WRITE_BYTE_ENABLE                             0xf358
#define CUNIT_READ_DATA_LOW                                 0xf350
#define CUNIT_READ_DATA_HIGH                                0xf354
#define CUNIT_READ_ID                                       0xf35c

/****************************************/
/* Fast Ethernet Unit Registers         */
/****************************************/

/* Ethernet */

#define ETH_PHY_ADDR_REG                               	0x2000
#define ETH_SMI_REG                                    	0x2010

#define	ETHERNET_PORTS_DIFFERENCE_OFFSETS		0x0400

/* Ethernet 0 */

#define ETH0_PORT_CONFIG_REG               		0x2400
#define ETH0_PORT_CONFIG_EXT_REG        		0x2408
#define ETH0_PORT_COMMAND_REG                     	0x2410
#define ETH0_PORT_STATUS_REG                      	0x2418
#define ETH0_SERIAL_PARAMETRS_REG                 	0x2420
#define ETH0_HASH_TABLE_PTR_REG               		0x2428
#define ETH0_FLOW_CONTROL_SOURCE_ADDR_LO           	0x2430
#define ETH0_FLOW_CONTROL_SOURCE_ADDR_HI          	0x2438
#define ETH0_SDMA_CONFIG_REG               		0x2440
#define ETH0_SDMA_COMMAND_REG                     	0x2448
#define ETH0_INTERRUPT_CAUSE_REG                  	0x2450
#define ETH0_INTERRUPT_MASK_REG                   	0x2458