gt64240reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/****************************************/
/*          Pslave Debug           	*/
/****************************************/

#define X_0_ADDRESS                                   	0x360
#define X_0_COMMAND_ID                                  0x368
#define X_1_ADDRESS                                     0x370
#define X_1_COMMAND_ID                                  0x378
#define WRITE_DATA_LOW                                  0x3c0
#define WRITE_DATA_HIGH                                 0x3c8
#define WRITE_BYTE_ENABLE                               0X3e0
#define READ_DATA_LOW                                   0x3d0
#define READ_DATA_HIGH                                  0x3d8
#define READ_ID                                         0x3e8


/****************************************/
/* SDRAM and Device Address Space	*/
/****************************************/
	

/****************************************/
/* SDRAM Configuration			*/
/****************************************/

#define SDRAM_CONFIGURATION	 			0x448
#define SDRAM_OPERATION_MODE				0x474
#define SDRAM_ADDRESS_DECODE				0x47c
#define SDRAM_UMA_CONTROL                               0x4a4
#define SDRAM_CROSS_BAR_CONTROL_LOW                     0x4a8
#define SDRAM_CROSS_BAR_CONTROL_HIGH                    0x4ac
#define SDRAM_CROSS_BAR_TIMEOUT                         0x4b0
#define	SDRAM_TIMING_PARAMETERS				0x4b4


/****************************************/
/* SDRAM Parameters			*/
/****************************************/
			
#define SDRAM_BANK0PARAMETERS				0x44C
#define SDRAM_BANK1PARAMETERS				0x450
#define SDRAM_BANK2PARAMETERS				0x454
#define SDRAM_BANK3PARAMETERS				0x458


/****************************************/
/* SDRAM Error Report 			*/
/****************************************/
			
#define SDRAM_ERROR_DATA_LOW                            0x484
#define SDRAM_ERROR_DATA_HIGH                           0x480
#define SDRAM_AND_DEVICE_ERROR_ADDRESS                  0x490
#define SDRAM_RECEIVED_ECC                              0x488
#define SDRAM_CALCULATED_ECC                            0x48c
#define SDRAM_ECC_CONTROL                               0x494
#define SDRAM_ECC_ERROR_COUNTER                         0x498


/****************************************/
/* SDunit Debug (for internal use)	*/
/****************************************/

#define X0_ADDRESS                                      0x500
#define X0_COMMAND_AND_ID                               0x504
#define X0_WRITE_DATA_LOW                               0x508
#define X0_WRITE_DATA_HIGH                              0x50c
#define X0_WRITE_BYTE_ENABLE                            0x518
#define X0_READ_DATA_LOW                                0x510
#define X0_READ_DATA_HIGH                               0x514
#define X0_READ_ID                                      0x51c
#define X1_ADDRESS                                      0x520
#define X1_COMMAND_AND_ID                               0x524
#define X1_WRITE_DATA_LOW                               0x528
#define X1_WRITE_DATA_HIGH                              0x52c
#define X1_WRITE_BYTE_ENABLE                            0x538
#define X1_READ_DATA_LOW                                0x530
#define X1_READ_DATA_HIGH                               0x534
#define X1_READ_ID                                      0x53c
#define X0_SNOOP_ADDRESS                                0x540
#define X0_SNOOP_COMMAND                                0x544
#define X1_SNOOP_ADDRESS                                0x548
#define X1_SNOOP_COMMAND                                0x54c

			

/****************************************/
/* Device Parameters			*/
/****************************************/

#define DEVICE_BANK0PARAMETERS				0x45c
#define DEVICE_BANK1PARAMETERS				0x460
#define DEVICE_BANK2PARAMETERS				0x464
#define DEVICE_BANK3PARAMETERS				0x468
#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
#define DEVICE_CONTROL                                  0x4c0
#define DEVICE_CROSS_BAR_CONTROL_LOW                    0x4c8
#define DEVICE_CROSS_BAR_CONTROL_HIGH                   0x4cc
#define DEVICE_CROSS_BAR_TIMEOUT                        0x4c4

/****************************************/
/* Device Interrupt 			*/
/****************************************/

#define DEVICE_INTERRUPT_CAUSE                          0x4d0
#define DEVICE_INTERRUPT_MASK                           0x4d4
#define DEVICE_ERROR_ADDRESS                            0x4d8

/****************************************/
/* DMA Record				*/
/****************************************/

#define CHANNEL0_DMA_BYTE_COUNT				0x800
#define CHANNEL1_DMA_BYTE_COUNT	 			0x804
#define CHANNEL2_DMA_BYTE_COUNT	 			0x808
#define CHANNEL3_DMA_BYTE_COUNT	 			0x80C
#define CHANNEL4_DMA_BYTE_COUNT				0x900
#define CHANNEL5_DMA_BYTE_COUNT	 			0x904
#define CHANNEL6_DMA_BYTE_COUNT	 			0x908
#define CHANNEL7_DMA_BYTE_COUNT	 			0x90C
#define CHANNEL0_DMA_SOURCE_ADDRESS			0x810
#define CHANNEL1_DMA_SOURCE_ADDRESS			0x814
#define CHANNEL2_DMA_SOURCE_ADDRESS			0x818
#define CHANNEL3_DMA_SOURCE_ADDRESS			0x81C
#define CHANNEL4_DMA_SOURCE_ADDRESS			0x910
#define CHANNEL5_DMA_SOURCE_ADDRESS			0x914
#define CHANNEL6_DMA_SOURCE_ADDRESS			0x918
#define CHANNEL7_DMA_SOURCE_ADDRESS			0x91C
#define CHANNEL0_DMA_DESTINATION_ADDRESS		0x820
#define CHANNEL1_DMA_DESTINATION_ADDRESS		0x824
#define CHANNEL2_DMA_DESTINATION_ADDRESS		0x828
#define CHANNEL3_DMA_DESTINATION_ADDRESS		0x82C
#define CHANNEL4_DMA_DESTINATION_ADDRESS		0x920
#define CHANNEL5_DMA_DESTINATION_ADDRESS		0x924
#define CHANNEL6_DMA_DESTINATION_ADDRESS		0x928
#define CHANNEL7_DMA_DESTINATION_ADDRESS		0x92C
#define CHANNEL0NEXT_RECORD_POINTER			0x830
#define CHANNEL1NEXT_RECORD_POINTER			0x834
#define CHANNEL2NEXT_RECORD_POINTER			0x838
#define CHANNEL3NEXT_RECORD_POINTER			0x83C
#define CHANNEL4NEXT_RECORD_POINTER			0x930
#define CHANNEL5NEXT_RECORD_POINTER			0x934
#define CHANNEL6NEXT_RECORD_POINTER			0x938
#define CHANNEL7NEXT_RECORD_POINTER			0x93C
#define CHANNEL0CURRENT_DESCRIPTOR_POINTER		0x870
#define CHANNEL1CURRENT_DESCRIPTOR_POINTER		0x874
#define CHANNEL2CURRENT_DESCRIPTOR_POINTER		0x878
#define CHANNEL3CURRENT_DESCRIPTOR_POINTER		0x87C
#define CHANNEL4CURRENT_DESCRIPTOR_POINTER		0x970
#define CHANNEL5CURRENT_DESCRIPTOR_POINTER		0x974
#define CHANNEL6CURRENT_DESCRIPTOR_POINTER		0x978
#define CHANNEL7CURRENT_DESCRIPTOR_POINTER		0x97C
#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS            0x890
#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS            0x894
#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS            0x898
#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS            0x89c
#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS            0x990
#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS            0x994
#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS            0x998
#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS            0x99c
#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS       0x8a0
#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS       0x8a4
#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS       0x8a8
#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS       0x8ac
#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS       0x9a0
#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS       0x9a4
#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS       0x9a8
#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS       0x9ac
#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b0
#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b4
#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b8
#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8bc
#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b0
#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b4
#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b8
#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9bc

/****************************************/
/* DMA Channel Control			*/
/****************************************/

#define CHANNEL0CONTROL 				0x840
#define CHANNEL0CONTROL_HIGH				0x880
#define CHANNEL1CONTROL 				0x844
#define CHANNEL1CONTROL_HIGH				0x884
#define CHANNEL2CONTROL 				0x848
#define CHANNEL2CONTROL_HIGH				0x888
#define CHANNEL3CONTROL 				0x84C
#define CHANNEL3CONTROL_HIGH				0x88C

#define CHANNEL4CONTROL 				0x940
#define CHANNEL4CONTROL_HIGH				0x980
#define CHANNEL5CONTROL 				0x944
#define CHANNEL5CONTROL_HIGH				0x984
#define CHANNEL6CONTROL 				0x948
#define CHANNEL6CONTROL_HIGH				0x988
#define CHANNEL7CONTROL 				0x94C
#define CHANNEL7CONTROL_HIGH				0x98C


/****************************************/
/* DMA Arbiter				*/
/****************************************/

#define ARBITER_CONTROL_0_3				0x860
#define ARBITER_CONTROL_4_7				0x960


/****************************************/
/* DMA Interrupt			*/
/****************************************/

#define CHANELS0_3_INTERRUPT_CAUSE                      0x8c0
#define CHANELS0_3_INTERRUPT_MASK                       0x8c4
#define CHANELS0_3_ERROR_ADDRESS                        0x8c8
#define CHANELS0_3_ERROR_SELECT                         0x8cc
#define CHANELS4_7_INTERRUPT_CAUSE                      0x9c0
#define CHANELS4_7_INTERRUPT_MASK                       0x9c4
#define CHANELS4_7_ERROR_ADDRESS                        0x9c8
#define CHANELS4_7_ERROR_SELECT                         0x9cc


/****************************************/
/* DMA Debug (for internal use)         */
/****************************************/

#define DMA_X0_ADDRESS                                  0x8e0
#define DMA_X0_COMMAND_AND_ID                           0x8e4
#define DMA_X0_WRITE_DATA_LOW                           0x8e8
#define DMA_X0_WRITE_DATA_HIGH                          0x8ec
#define DMA_X0_WRITE_BYTE_ENABLE                        0x8f8
#define DMA_X0_READ_DATA_LOW                            0x8f0
#define DMA_X0_READ_DATA_HIGH                           0x8f4
#define DMA_X0_READ_ID                                  0x8fc
#define DMA_X1_ADDRESS                                  0x9e0
#define DMA_X1_COMMAND_AND_ID                           0x9e4
#define DMA_X1_WRITE_DATA_LOW                           0x9e8
#define DMA_X1_WRITE_DATA_HIGH                          0x9ec
#define DMA_X1_WRITE_BYTE_ENABLE                        0x9f8
#define DMA_X1_READ_DATA_LOW                            0x9f0
#define DMA_X1_READ_DATA_HIGH                           0x9f4
#define DMA_X1_READ_ID                                  0x9fc

/****************************************/
/* Timer_Counter 			*/
/****************************************/

#define TIMER_COUNTER0					0x850
#define TIMER_COUNTER1					0x854
#define TIMER_COUNTER2					0x858
#define TIMER_COUNTER3					0x85C
#define TIMER_COUNTER_0_3_CONTROL			0x864
#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE		0x868
#define TIMER_COUNTER_0_3_INTERRUPT_MASK      		0x86c
#define TIMER_COUNTER4					0x950
#define TIMER_COUNTER5					0x954
#define TIMER_COUNTER6					0x958
#define TIMER_COUNTER7					0x95C
#define TIMER_COUNTER_4_7_CONTROL			0x964
#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE		0x968
#define TIMER_COUNTER_4_7_INTERRUPT_MASK      		0x96c

/****************************************/
/* PCI Slave Address Decoding           */
/****************************************/