mv64340reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#define DFCDL_PROBE					0x14a0

/****************************************/
/* SDRAM Error Report 			*/
/****************************************/
			
#define SDRAM_ERROR_DATA_LOW                            0x484
#define SDRAM_ERROR_DATA_HIGH                           0x480
#define SDRAM_AND_DEVICE_ERROR_ADDRESS                  0x490
#define SDRAM_RECEIVED_ECC                              0x488
#define SDRAM_CALCULATED_ECC                            0x48c
#define SDRAM_ECC_CONTROL                               0x494
#define SDRAM_ECC_ERROR_COUNTER                         0x498


/****************************************/
/* SDunit Debug (for internal use)	*/
/****************************************/

#define X0_ADDRESS                                      0x500
#define X0_COMMAND_AND_ID                               0x504
#define X0_WRITE_DATA_LOW                               0x508
#define X0_WRITE_DATA_HIGH                              0x50c
#define X0_WRITE_BYTE_ENABLE                            0x518
#define X0_READ_DATA_LOW                                0x510
#define X0_READ_DATA_HIGH                               0x514
#define X0_READ_ID                                      0x51c
#define X1_ADDRESS                                      0x520
#define X1_COMMAND_AND_ID                               0x524
#define X1_WRITE_DATA_LOW                               0x528
#define X1_WRITE_DATA_HIGH                              0x52c
#define X1_WRITE_BYTE_ENABLE                            0x538
#define X1_READ_DATA_LOW                                0x530
#define X1_READ_DATA_HIGH                               0x534
#define X1_READ_ID                                      0x53c
#define X0_SNOOP_ADDRESS                                0x540
#define X0_SNOOP_COMMAND                                0x544
#define X1_SNOOP_ADDRESS                                0x548
#define X1_SNOOP_COMMAND                                0x54c

			

/****************************************/
/* Device Parameters			*/
/****************************************/

/* MDD: This section done */

#define DEVICE_BANK0PARAMETERS				0x45c
#define DEVICE_BANK1PARAMETERS				0x460
#define DEVICE_BANK2PARAMETERS				0x464
#define DEVICE_BANK3PARAMETERS				0x468
#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
#define DEVICE_CONTROL                                  0x4c0
#define DEVICE_CROSS_BAR_CONTROL_LOW                    0x4c8
#define DEVICE_CROSS_BAR_CONTROL_HIGH                   0x4cc
#define DEVICE_CROSS_BAR_TIMEOUT                        0x4c4

/****************************************/
/* Device Interrupt 			*/
/****************************************/

#define DEVICE_INTERRUPT_CAUSE                          0x4d0
#define DEVICE_INTERRUPT_MASK                           0x4d4
#define DEVICE_ERROR_ADDRESS                            0x4d8

/****************************************/
/* DMA Record				*/
/****************************************/

#define CHANNEL0_DMA_BYTE_COUNT				0x800
#define CHANNEL1_DMA_BYTE_COUNT	 			0x804
#define CHANNEL2_DMA_BYTE_COUNT	 			0x808
#define CHANNEL3_DMA_BYTE_COUNT	 			0x80C
#define CHANNEL0_DMA_SOURCE_ADDRESS			0x810
#define CHANNEL1_DMA_SOURCE_ADDRESS			0x814
#define CHANNEL2_DMA_SOURCE_ADDRESS			0x818
#define CHANNEL3_DMA_SOURCE_ADDRESS			0x81C
#define CHANNEL0_DMA_DESTINATION_ADDRESS		0x820
#define CHANNEL1_DMA_DESTINATION_ADDRESS		0x824
#define CHANNEL2_DMA_DESTINATION_ADDRESS		0x828
#define CHANNEL3_DMA_DESTINATION_ADDRESS		0x82C
#define CHANNEL0NEXT_RECORD_POINTER			0x830
#define CHANNEL1NEXT_RECORD_POINTER			0x834
#define CHANNEL2NEXT_RECORD_POINTER			0x838
#define CHANNEL3NEXT_RECORD_POINTER			0x83C
#define CHANNEL0CURRENT_DESCRIPTOR_POINTER		0x870
#define CHANNEL1CURRENT_DESCRIPTOR_POINTER		0x874
#define CHANNEL2CURRENT_DESCRIPTOR_POINTER		0x878
#define CHANNEL3CURRENT_DESCRIPTOR_POINTER		0x87C

/****************************************/
/* DMA Channel Control			*/
/****************************************/

#define CHANNEL0CONTROL 				0x840
#define CHANNEL0CONTROL_HIGH				0x880
#define CHANNEL1CONTROL 				0x844
#define CHANNEL1CONTROL_HIGH				0x884
#define CHANNEL2CONTROL 				0x848
#define CHANNEL2CONTROL_HIGH				0x888
#define CHANNEL3CONTROL 				0x84C
#define CHANNEL3CONTROL_HIGH				0x88C

/****************************************/
/* DMA Arbiter				*/
/****************************************/

#define ARBITER_CONTROL_0_3				0x860
#define ARBITER_CONTROL_4_7				0x960


/****************************************/
/* DMA Interrupt			*/
/****************************************/

#define CHANELS0_3_INTERRUPT_CAUSE                      0x8c0
#define CHANELS0_3_INTERRUPT_MASK                       0x8c4
#define CHANELS0_3_ERROR_ADDRESS                        0x8c8
#define CHANELS0_3_ERROR_SELECT                         0x8cc
#define CHANELS4_7_INTERRUPT_CAUSE                      0x9c0
#define CHANELS4_7_INTERRUPT_MASK                       0x9c4
#define CHANELS4_7_ERROR_ADDRESS                        0x9c8
#define CHANELS4_7_ERROR_SELECT                         0x9cc


/****************************************/
/* DMA Debug (for internal use)         */
/****************************************/

#define DMA_X0_ADDRESS                                  0x8e0
#define DMA_X0_COMMAND_AND_ID                           0x8e4
#define DMA_X0_WRITE_DATA_LOW                           0x8e8
#define DMA_X0_WRITE_DATA_HIGH                          0x8ec
#define DMA_X0_WRITE_BYTE_ENABLE                        0x8f8
#define DMA_X0_READ_DATA_LOW                            0x8f0
#define DMA_X0_READ_DATA_HIGH                           0x8f4
#define DMA_X0_READ_ID                                  0x8fc
#define DMA_X1_ADDRESS                                  0x9e0
#define DMA_X1_COMMAND_AND_ID                           0x9e4
#define DMA_X1_WRITE_DATA_LOW                           0x9e8
#define DMA_X1_WRITE_DATA_HIGH                          0x9ec
#define DMA_X1_WRITE_BYTE_ENABLE                        0x9f8
#define DMA_X1_READ_DATA_LOW                            0x9f0
#define DMA_X1_READ_DATA_HIGH                           0x9f4
#define DMA_X1_READ_ID                                  0x9fc

/****************************************/
/* Timer_Counter 			*/
/****************************************/

#define TIMER_COUNTER0					0x850
#define TIMER_COUNTER1					0x854
#define TIMER_COUNTER2					0x858
#define TIMER_COUNTER3					0x85C
#define TIMER_COUNTER_0_3_CONTROL			0x864
#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE		0x868
#define TIMER_COUNTER_0_3_INTERRUPT_MASK      		0x86c

/****************************************/
/* PCI Slave Address Decoding           */
/****************************************/

/* MDD This section done */
        
#define PCI_0SCS_0_BANK_SIZE				0xc08
#define PCI_1SCS_0_BANK_SIZE				0xc88
#define PCI_0SCS_1_BANK_SIZE				0xd08
#define PCI_1SCS_1_BANK_SIZE				0xd88
#define PCI_0SCS_2_BANK_SIZE				0xc0c
#define PCI_1SCS_2_BANK_SIZE				0xc8c
#define PCI_0SCS_3_BANK_SIZE				0xd0c
#define PCI_1SCS_3_BANK_SIZE				0xd8c
#define PCI_0CS_0_BANK_SIZE				0xc10
#define PCI_1CS_0_BANK_SIZE				0xc90
#define PCI_0CS_1_BANK_SIZE				0xd10
#define PCI_1CS_1_BANK_SIZE				0xd90
#define PCI_0CS_2_BANK_SIZE				0xd18
#define PCI_1CS_2_BANK_SIZE				0xd98
#define PCI_0CS_3_BANK_SIZE				0xc14
#define PCI_1CS_3_BANK_SIZE				0xc94
#define PCI_0CS_BOOT_BANK_SIZE				0xd14
#define PCI_1CS_BOOT_BANK_SIZE				0xd94
#define PCI_0P2P_MEM0_BAR_SIZE                          0xd1c
#define PCI_1P2P_MEM0_BAR_SIZE                          0xd9c
#define PCI_0P2P_MEM1_BAR_SIZE                          0xd20
#define PCI_1P2P_MEM1_BAR_SIZE                          0xda0
#define PCI_0P2P_I_O_BAR_SIZE                           0xd24
#define PCI_1P2P_I_O_BAR_SIZE                           0xda4
#define PCI_0INTERNAL_SRAM_BAR_SIZE                     0xe00
#define PCI_1INTERNAL_SRAM_BAR_SIZE                     0xe80
#define PCI_0EXPANSION_ROM_BAR_SIZE                     0xd2c
#define PCI_1EXPANSION_ROM_BAR_SIZE                     0xdac
#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 		0xc3c
#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 		0xcbc
#define PCI_0SCS_0_BASE_ADDRESS_REMAP			0xc48
#define PCI_1SCS_0_BASE_ADDRESS_REMAP			0xcc8
#define PCI_0SCS_1_BASE_ADDRESS_REMAP			0xd48
#define PCI_1SCS_1_BASE_ADDRESS_REMAP			0xdc8
#define PCI_0SCS_2_BASE_ADDRESS_REMAP			0xc4c
#define PCI_1SCS_2_BASE_ADDRESS_REMAP			0xccc
#define PCI_0SCS_3_BASE_ADDRESS_REMAP			0xd4c
#define PCI_1SCS_3_BASE_ADDRESS_REMAP			0xdcc
#define PCI_0CS_0_BASE_ADDRESS_REMAP			0xc50
#define PCI_1CS_0_BASE_ADDRESS_REMAP			0xcd0
#define PCI_0CS_1_BASE_ADDRESS_REMAP			0xd50
#define PCI_1CS_1_BASE_ADDRESS_REMAP			0xdd0
#define PCI_0CS_2_BASE_ADDRESS_REMAP			0xd58
#define PCI_1CS_2_BASE_ADDRESS_REMAP			0xdd8
#define PCI_0CS_3_BASE_ADDRESS_REMAP           		0xc54
#define PCI_1CS_3_BASE_ADDRESS_REMAP           		0xcd4
#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP      		0xd54
#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP      		0xdd4
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xd5c
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xddc
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xd60
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xde0
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xd64
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xde4
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xd68
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xde8
#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP                 0xd6c
#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP                 0xdec
#define PCI_0INTERNAL_SRAM_BASE_ADDRESS_REMAP		    0xf00
#define PCI_1INTERNAL_SRAM_BASE_ADDRESS_REMAP		    0xf80
#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP               0xf38
#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP               0xfb8
#define PCI_0ADDRESS_DECODE_CONTROL                         0xd3c
#define PCI_1ADDRESS_DECODE_CONTROL                         0xdbc

/****************************************/
/* PCI Control                          */
/****************************************/

#define PCI0_DLL_STATUS_CONTROL					0x1d20
#define PCI1_DLL_STATUS_CONTROL					0x1da0
#define PCI0_PADS_CALIBRATION					0x1d1c
#define PCI1_PADS_CALIBRATION					0x1d9c

#define PCI_0COMMAND					    0xc00
#define PCI_1COMMAND					    0xc80
#define PCI_0MODE                                           0xd00
#define PCI_1MODE                                           0xd80
#define PCI_0TIMEOUT_RETRY				    0xc04
#define PCI_1TIMEOUT_RETRY				    0xc84
#define PCI_0READ_BUFFER_DISCARD_TIMER                      0xd04
#define PCI_1READ_BUFFER_DISCARD_TIMER                      0xd84
#define MSI_0TRIGGER_TIMER                                  0xc38
#define MSI_1TRIGGER_TIMER                                  0xcb8
#define PCI_0ARBITER_CONTROL                                0x1d00
#define PCI_1ARBITER_CONTROL                                0x1d80

/* changed until here */
#define PCI_0CROSS_BAR_CONTROL_LOW                           0x1d08
#define PCI_0CROSS_BAR_CONTROL_HIGH                          0x1d0c
#define PCI_0CROSS_BAR_TIMEOUT                               0x1d04
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d18
#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d10
#define PCI_0P2P_CONFIGURATION                               0x1d14
#define PCI_0ACCESS_CONTROL_BASE_0_LOW                       0x1e00
#define PCI_0ACCESS_CONTROL_BASE_0_HIGH                      0x1e04
#define PCI_0ACCESS_CONTROL_TOP_0                            0x1e08
#define PCI_0ACCESS_CONTROL_BASE_1_LOW                       0c1e10
#define PCI_0ACCESS_CONTROL_BASE_1_HIGH                      0x1e14
#define PCI_0ACCESS_CONTROL_TOP_1                            0x1e18
#define PCI_0ACCESS_CONTROL_BASE_2_LOW                       0c1e20
#define PCI_0ACCESS_CONTROL_BASE_2_HIGH                      0x1e24
#define PCI_0ACCESS_CONTROL_TOP_2                            0x1e28
#define PCI_0ACCESS_CONTROL_BASE_3_LOW                       0c1e30
#define PCI_0ACCESS_CONTROL_BASE_3_HIGH                      0x1e34
#define PCI_0ACCESS_CONTROL_TOP_3                            0x1e38
#define PCI_0ACCESS_CONTROL_BASE_4_LOW                       0c1e40
#define PCI_0ACCESS_CONTROL_BASE_4_HIGH                      0x1e44
#define PCI_0ACCESS_CONTROL_TOP_4                            0x1e48
#define PCI_0ACCESS_CONTROL_BASE_5_LOW                       0c1e50
#define PCI_0ACCESS_CONTROL_BASE_5_HIGH                      0x1e54
#define PCI_0ACCESS_CONTROL_TOP_5                            0x1e58
#define PCI_0ACCESS_CONTROL_BASE_6_LOW                       0c1e60
#define PCI_0ACCESS_CONTROL_BASE_6_HIGH                      0x1e64
#define PCI_0ACCESS_CONTROL_TOP_6                            0x1e68
#define PCI_0ACCESS_CONTROL_BASE_7_LOW                       0c1e70
#define PCI_0ACCESS_CONTROL_BASE_7_HIGH                      0x1e74
#define PCI_0ACCESS_CONTROL_TOP_7                            0x1e78
#define PCI_1CROSS_BAR_CONTROL_LOW                           0x1d88
#define PCI_1CROSS_BAR_CONTROL_HIGH                          0x1d8c
#define PCI_1CROSS_BAR_TIMEOUT                               0x1d84
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d98
#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d90
#define PCI_1P2P_CONFIGURATION                               0x1d94
#define PCI_1ACCESS_CONTROL_BASE_0_LOW                       0x1e80
#define PCI_1ACCESS_CONTROL_BASE_0_HIGH                      0x1e84
#define PCI_1ACCESS_CONTROL_TOP_0                            0x1e88
#define PCI_1ACCESS_CONTROL_BASE_1_LOW                       0c1e90
#define PCI_1ACCESS_CONTROL_BASE_1_HIGH                      0x1e94
#define PCI_1ACCESS_CONTROL_TOP_1                            0x1e98