mv64340reg.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/* $Id: mv64340reg.h,v 1.5 2002/08/30 00:01:29 mdharm Exp $ */

/*
 * Copyright (c) 2001-2002 Galileo Technology.
 * Copyright (c) 2002 Momentum Computer.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Galileo Technology.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */
/* mv64340reg.h - MV-64340 Internal registers definition file */

#ifndef _MV64340REG_H_
#define _MV64340REG_H_

#ifdef __MIPSEB__
#define HTOLE32(v)      ((((v) & 0xff) << 24) | (((v) & 0xff00) << 8) | \
                        (((v) >> 24) & 0xff) | (((v) >> 8) & 0xff00))
#else
#ifdef __MIPSEL__
#define HTOLE32(v)      (v)
#else
#error ENDIAN NOT DEFINED!
#endif
#endif

#define GT_WRITE(ofs, data) \
    *(volatile u_int32_t *)(GT_BASE_ADDR+ofs) = HTOLE32(data)

#define GT_READ(ofs) \
    HTOLE32(*(volatile u_int32_t *)(GT_BASE_ADDR+ofs))

#define GT_BASE_ADDR			PHYS_TO_IOSPACE(0x14000000)
#define GT_BASE_ADDR_DEFAULT		PHYS_TO_UNCACHED(0x14000000)


/************************************************/
#define GT_DEVPAR_TurnOff(x)            ((((x) & 7) << 0) | (((x) & 8) << 19))
#define GT_DEVPAR_AccToFirst(x)         ((((x) & 15) << 3) | (((x) & 16) << 19))
#define GT_DEVPAR_AccToNext(x)          ((((x) & 15) << 7) | (((x) & 16) << 20))
#define GT_DEVPAR_ALEtoWr(x)            ((((x) & 7) << 11) | (((x) & 8) << 22))
#define GT_DEVPAR_WrActive(x)           ((((x) & 7) << 14) | (((x) & 8) << 23))
#define GT_DEVPAR_WrHigh(x)             ((((x) & 7) << 17) | (((x) & 8) << 24))
#define GT_DEVPAR_DevWidth8             (0<<20)
#define GT_DEVPAR_DevWidth16            (1<<20)
#define GT_DEVPAR_DevWidth32            (2<<20)
#define	GT_DEVPAR_DevWidthMASK		(3<<20)
#define GT_DEVPAR_BaddrSkew0            (0<<28)
#define GT_DEVPAR_BaddrSkew1            (1<<28)
#define GT_DEVPAR_BaddrSkew2            (2<<28)
#define GT_DEVPAR_BaddrSkewMASK         (3<<28)
#define GT_DEVPAR_DPEnDisable           (0<<30)
#define GT_DEVPAR_DPEnEnable            (1<<30)
#define GT_DEVPAR_ReservedMASK          0x80000000
#define GT_DEVPAR_Reserved              0x80000000 

/* MDD: Done to here */

/************************************************/
#define GT_PCI0_MAP10                   0x0010
#define GT_PCI0_MAP14                   0x0014
#define GT_PCI1_MAP10                   0x0090
#define GT_PCI1_MAP14                   0x0094
/************************************************/
#define GT_IPCI_CFGADDR_ConfigEn        (1<<31)
/************************************************/
#define GT_SMIR_REG			0x2010
#define CPU_CONF        		0x0000
#define SDRAM_CNFG      		0x0448
#define SDRAM_PARA0     		0x044c
#define SDRAM_PARA1     		0x0450
#define SDRAM_PARA2     		0x0454
#define SDRAM_PARA3     		0x0458
#define GT_DEV0_PAR     		0x045c
#define GT_DEV1_PAR     		0x0460
#define GT_DEV2_PAR     		0x0464
#define GT_DEV3_PAR     		0x0468
#define GT_BOOT_PAR     		0x046c
#define PCI0_COMMAND    		0x0c00
#define PCI1_COMMAND    		0x0c80
#define PCI0_IO_LO      		0x0048
#define PCI0_IO_HI      		0x0050
#define PCI0_MEM0_LO    		0x0058
#define PCI0_MEM0_HI    		0x0060
#define PCI1_IO_LO     			0x0090
#define PCI1_IO_HI      		0x0098
#define PCI1_MEM0_LO    		0x00a0
#define PCI1_MEM0_HI    		0x00a8
#define CPU_CONFIG      		0x0000
#define SCS0_LOW 	     		0x0008
#define SCS0_HIGH 	    		0x0010
#define SCS2_LOW 	     		0x0018
#define SCS2_HIGH 	    		0x0020
#define SCS1_LOW        		0x0208
#define SCS1_HIGH       		0x0210
#define SCS3_LOW        		0x0218
#define SCS3_HIGH       		0x0220
#define PCI_1_IO_LOW    		0x0090
#define PCI_1_IO_HIGH   		0x0098
#define PCI1_MEM0_LOW   		0x00a0
#define PCI1_MEM0_HIGH  		0x00a8
#define PCI_1_MEM1_LOW  		0x00b0
#define PCI_1_MEM1_HIGH 		0x00b8
#define PCI_0_TIME_OUT  		0x0c04
#define PCI_1_TIME_OUT  		0x0c84
#define PCI_0_BAR_EN    		0x0c3c
#define PCI_1_BAR_EN    		0x0cbc
#define PCI_0_ARBITER   		0x1d00
#define PCI_1_ARBITER   		0x1d80
#define MPP_CNTRL0      		0xf000
#define MPP_CNTRL1      		0xf004
#define MPP_CNTRL2      		0xf008
#define MPP_CNTRL3      		0xf00c
#define SER_PORTS_MUX   		0xf010

/****************************************/
/* Processor Address Space		*/
/****************************************/

/* MDD: This section done */

/* BAR Enables */
#define CPU_BASE_ADDRESS_ENABLE				0x278

/* Sdram's BAR'S */
#define SCS_0_BASE_ADDRESS				0x008
#define SCS_0_SIZE					0x010
#define SCS_1_BASE_ADDRESS				0x208
#define SCS_1_SIZE					0x210
#define SCS_2_BASE_ADDRESS				0x018
#define SCS_2_SIZE					0x020
#define SCS_3_BASE_ADDRESS				0x218
#define SCS_3_SIZE					0x220

/* Devices BAR'S */
#define CS_0_BASE_ADDRESS				0x028
#define CS_0_SIZE					0x030
#define CS_1_BASE_ADDRESS			    	0x228
#define CS_1_SIZE					0x230
#define CS_2_BASE_ADDRESS			    	0x248
#define CS_2_SIZE					0x250
#define CS_3_BASE_ADDRESS				0x038
#define CS_3_SIZE					0x040
#define BOOTCS_BASE_ADDRESS				0x238
#define BOOTCS_SIZE					0x240

#define PCI_0I_O_BASE_ADDRESS				0x048
#define PCI_0I_O_SIZE					0x050
#define PCI_0MEMORY0_BASE_ADDRESS			0x058
#define PCI_0MEMORY0_SIZE				0x060
#define PCI_0MEMORY1_BASE_ADDRESS			0x080
#define PCI_0MEMORY1_SIZE				0x088
#define PCI_0MEMORY2_BASE_ADDRESS			0x258
#define PCI_0MEMORY2_SIZE				0x260
#define PCI_0MEMORY3_BASE_ADDRESS			0x280
#define PCI_0MEMORY3_SIZE				0x288

#define PCI_1I_O_BASE_ADDRESS				0x090
#define PCI_1I_O_SIZE					0x098
#define PCI_1MEMORY0_BASE_ADDRESS			0x0a0
#define PCI_1MEMORY0_SIZE				0x0a8
#define PCI_1MEMORY1_BASE_ADDRESS			0x0b0
#define PCI_1MEMORY1_SIZE				0x0b8
#define PCI_1MEMORY2_BASE_ADDRESS			0x2a0
#define PCI_1MEMORY2_SIZE				0x2a8
#define PCI_1MEMORY3_BASE_ADDRESS			0x2b0
#define PCI_1MEMORY3_SIZE				0x2b8

#define INTERNAL_SPACE_BASE				0x068
#define INTERNAL_SRAM_BASE				0x268

#define PCI_0I_O_ADDRESS_REMAP				0x0f0
#define PCI_0MEMORY0_ADDRESS_REMAP  			0x0f8
#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP			0x320
#define PCI_0MEMORY1_ADDRESS_REMAP  			0x100
#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP			0x328
#define PCI_0MEMORY2_ADDRESS_REMAP  			0x2f8
#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP			0x330
#define PCI_0MEMORY3_ADDRESS_REMAP  			0x300
#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP			0x338

#define PCI_1I_O_ADDRESS_REMAP				0x108
#define PCI_1MEMORY0_ADDRESS_REMAP  			0x110
#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP			0x340
#define PCI_1MEMORY1_ADDRESS_REMAP  			0x118
#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP			0x348
#define PCI_1MEMORY2_ADDRESS_REMAP  			0x310
#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP			0x350
#define PCI_1MEMORY3_ADDRESS_REMAP  			0x318
#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP			0x358


/****************************************/
/* CPU Sync Barrier             	*/
/****************************************/

#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER		0x0c0
#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER		0x0c8


/****************************************/
/* CPU Access Protect             	*/
/****************************************/

#define CPU_LOW_PROTECT_ADDRESS_0                     	0x180
#define CPU_HIGH_PROTECT_ADDRESS_0                      0x188
#define CPU_LOW_PROTECT_ADDRESS_1                       0x190
#define CPU_HIGH_PROTECT_ADDRESS_1                      0x198
#define CPU_LOW_PROTECT_ADDRESS_2                       0x1a0
#define CPU_HIGH_PROTECT_ADDRESS_2                      0x1a8
#define CPU_LOW_PROTECT_ADDRESS_3                       0x1b0
#define CPU_HIGH_PROTECT_ADDRESS_3                      0x1b8

/****************************************/
/*          CPU Error Report       	*/
/****************************************/

#define CPU_BUS_ERROR_LOW_ADDRESS 			0x070
#define CPU_BUS_ERROR_HIGH_ADDRESS 			0x078
#define CPU_BUS_ERROR_LOW_DATA                          0x128
#define CPU_BUS_ERROR_HIGH_DATA                         0x130
#define CPU_BUS_ERROR_LOW_PARITY                        0x138
#define CPU_BUS_ERROR_HIGH_PARITY                       0x140
#define CPU_BUS_ERROR_MASK                              0x148

/****************************************/
/*          Pslave Debug           	*/
/****************************************/

#define X_0_ADDRESS                                   	0x360
#define X_0_COMMAND_ID                                  0x368
#define X_1_ADDRESS                                     0x370
#define X_1_COMMAND_ID                                  0x378
#define WRITE_DATA_LOW                                  0x3c0
#define WRITE_DATA_HIGH                                 0x3c8
#define WRITE_BYTE_ENABLE                               0X3e0
#define READ_DATA_LOW                                   0x3d0
#define READ_DATA_HIGH                                  0x3d8
#define READ_ID                                         0x3e8


/****************************************/
/* SDRAM and Device Address Space	*/
/****************************************/
	

/****************************************/
/* SDRAM Configuration			*/
/****************************************/

/* MDD This section done */

#define SDRAM_CONFIGURATION	 			0x1400
#define DUNIT_CONTROL_LOW				0x1404
#define DUNIT_CONTROL_HIGH				0x1424
#define SDRAM_TIMING_LOW				0x1408
#define SDRAM_TIMING_HIGH				0x140c
#define SDRAM_ADDRESS_CONTROL				0x1410
#define SDRAM_OPEN_PAGES_CONTROL			0x1414
#define SDRAM_OPERATION					0x1418
#define SDRAM_MODE					0x141c
#define SDRAM_XTENDED_MODE				0x1420
#define SDRAM_CROSSBAR_CONTROL_LOW			0x1430
#define SDRAM_CROSSBAR_CONTROL_HIGH			0x1434
#define SDRAM_CROSSBAR_TIMEOUT				0x1438
#define SDRAM_ADDRESS_PADS_CALIBRATION			0x14c0
#define SDRAM_DATA_PADS_CALIBRATION			0x14c4

#define DFCDL_CONFIGURATION0				0x1480
#define DFCDL_CONFIGURATION1				0x1484
#define SRAM_ADDRESS					0x1490
#define SRAM_DATA0					0x1494