powerpc.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*
 *  Default Exception Vector Code copied to vector area at startup.
 */

	.text
	.globl	trapcode
trapcode:
	mtsprg	1, r1	 		/* Save SP */
	CPUINFOADDR(r1)
	stmw	r28, TEMPSAVE(r1)	/* Save registers R28-R31 */
	mflr	r28	 		/* Save LR */
	mfcr	r29	 		/* Save CR */

	mfsrr0	r30	 		/* PC */
	mfsrr1	r31	 		/* SR */
	bla	trap_catch 		/* Go do trap processing */

	.globl	trapsize
trapsize = .-trapcode

/*
 *  DSI and ISI trap handlers for excercising the BAT maping regs.
 *  This code is moved down to respecive vector when in PMON mode.
 */
	.globl	isitrap, isisize
isitrap:
	mtsprg	1, r1			/* Save SP */
	CPUINFOADDR(r1)
	stmw	r28, DISISAVE(r1)	/* free up a couple of regs */
	mflr	r28
	mfcr	r29
	mfsrr1	r31
	mtcr	r31
	bc	12, 17, 1f		/* PSL_PR set (should not) */

	mfsrr0	r31			/* Fault address */
	rlwinm	r31, r31, 7, 25, 28	/* Get segment nr * 8 */
	addis	r31, r31, HIADJ(battable)
	lwz	r30, LO(battable)(r31)
	mtcr	r30
	bc	4, 30, 1f		/* Not a valid sement */

	addi	r31, r31, 4		/* Yes, this is correct, don't change */
	lwz	r31, LO(battable)(r31)
	mtibatu	3, r30
	mtibatl 3, r31

	mtcr	r29
	lmw	r28, DISISAVE(r1)
	mfsprg	r1, 1			/* Restore SP */
	rfi

1:
	mtcr	r29
	lmw	r28, DISISAVE(r1)
	stmw	r28, TEMPSAVE(r1)	/* Save registers R28-R31 */
	mflr	r28			/* Save LR */
	mfcr	r29			/* Save CR */

	mfsrr0	r30			/* PC */
	mfsrr1	r31			/* SR */
	bla	trap_catch		/* Go do trap processing */
isisize = .-isitrap

	.globl	dsitrap, dsisize
dsitrap:
	mtsprg	1, r1			/* Save SP */
	CPUINFOADDR(r1)
	stmw	r28, DISISAVE(r1)	/* free up a couple of regs */
	mfcr	r29
	mfxer	r30
	mtsprg	2, r30
	mfsrr1	r31
	mtcr	r31
	bc	12, 17, 1f		/* PSL_PR set (should not) */

	mfdar	r31			/* Fault address */
	rlwinm	r31, r31, 7, 25, 28	/* Get segment nr * 8 */
	addis	r31, r31, HIADJ(battable)
	lwz	r30, LO(battable)(r31)
	mtcr	r30
	bc	4, 30, 1f		/* Not a valid sement */

	addi	r31, r31, 4		/* Yes, this is correct, don't change */
	lwz	r31, LO(battable)(r31)
	mtdbatu	3, r30
	mtdbatl 3, r31

	mfsprg	r30, 2
	mtxer	r30
	mtcr	r29
	lmw	r28, DISISAVE(r1)
	mfsprg	r1, 1			/* Restore SP */
	rfi

1:
	mtcr	r29
	mfsprg	r30, 2
	mtxer	r30
	lmw	r28, DISISAVE(r1)
	stmw	r28, TEMPSAVE(r1)	/* Save registers R28-R31 */
	mflr	r28			/* Save LR */
	mfcr	r29

	mfsrr0	r30			/* PC */
	mfsrr1	r31			/* SR */
	bla	trap_catch		/* Go do trap processing */
dsisize = .-dsitrap


/*
 *  Floating point save/restore.
 *
 *  fprestore(&fpsavearea);
 *  fpsave(&fpsavearea);
 */
	.text
	.globl	md_fprestore
md_fprestore:
	mfmsr	r4
	ori	r5, r4, PSL_FP
	mtmsr	r5
	isync
	addi	r3, r3, 64*4		/* Offset in frame to float registers */
	lfd	f0, -8(r3)
	mtfsf	0xff, f0
	lfd	f0, 0(r3)
	lfd	f1, 8(r3)
	lfd	f2, 16(r3)
	lfd	f3, 24(r3)
	lfd	f4, 32(r3)
	lfd	f5, 40(r3)
	lfd	f6, 48(r3)
	lfd	f7, 56(r3)
	lfd	f8, 64(r3)
	lfd	f9, 72(r3)
	lfd	f10, 80(r3)
	lfd	f11, 88(r3)
	lfd	f12, 96(r3)
	lfd	f13, 104(r3)
	lfd	f14, 112(r3)
	lfd	f15, 120(r3)
	lfd	f16, 128(r3)
	lfd	f17, 136(r3)
	lfd	f18, 144(r3)
	lfd	f19, 152(r3)
	lfd	f20, 160(r3)
	lfd	f21, 168(r3)
	lfd	f22, 176(r3)
	lfd	f23, 184(r3)
	lfd	f24, 192(r3)
	lfd	f25, 200(r3)
	lfd	f26, 208(r3)
	lfd	f27, 216(r3)
	lfd	f28, 224(r3)
	lfd	f29, 232(r3)
	lfd	f30, 240(r3)
	lfd	f31, 248(r3)
	mtmsr	r4
	isync
	blr

	.text
	.globl	md_fpsave
md_fpsave:
	mfmsr	r4
	ori	r5, r4, PSL_FP
	mtmsr	r5
	isync
	addi	r3, r3, 64*4		/* Offset in frame to float registers */
	stfd	f0, 0(r3)
	stfd	f1, 8(r3)
	stfd	f2, 16(r3)
	stfd	f3, 24(r3)
	stfd	f4, 32(r3)
	stfd	f5, 40(r3)
	stfd	f6, 48(r3)
	stfd	f7, 56(r3)
	stfd	f8, 64(r3)
	stfd	f9, 72(r3)
	stfd	f10, 80(r3)
	stfd	f11, 88(r3)
	stfd	f12, 96(r3)
	stfd	f13, 104(r3)
	stfd	f14, 112(r3)
	stfd	f15, 120(r3)
	stfd	f16, 128(r3)
	stfd	f17, 136(r3)
	stfd	f18, 144(r3)
	stfd	f19, 152(r3)
	stfd	f20, 160(r3)
	stfd	f21, 168(r3)
	stfd	f22, 176(r3)
	stfd	f23, 184(r3)
	stfd	f24, 192(r3)
	stfd	f25, 200(r3)
	stfd	f26, 208(r3)
	stfd	f27, 216(r3)
	stfd	f28, 224(r3)
	stfd	f29, 232(r3)
	stfd	f30, 240(r3)
	stfd	f31, 248(r3)
	mffs	f0
	stfd	f0, -8(r3)
	mtmsr	r4
	isync
	blr

/*
 *  Function to do 64 bit accesses using FP regs.
 *  Needed by Flash programming code.
 *
 *  movequad(u_int64_t *where, u_int64_t *what);
 */
	.text
	.globl	movequad
movequad:
	mfmsr	r5
	ori	r6, r5, PSL_FP
	mtmsr	r6
	isync

	lfd	f0, 0(r4)
	stfd	f0, 0(r3)

	mtmsr	r5
	isync
	blr

/*
 *  Execute 1000000 instructions.
 */
	.text
	.globl	loopforameg
loopforameg:
	lis	r0, 0x000f
	ori	r0, r0, 0x4240-4
	mtctr	r0
1:
	bdnz	1b
	blr

/*
 *  Loop for N instructions
 */
	.text
	.globl	loopNinstr
loopNinstr:
	mtctr	r3
1:
	bdnz	1b
	blr

/*
 *  Returns address to this CPUs cpuinfo area.
 */
	.globl	md_getcpuinfoptr
md_getcpuinfoptr:
	CPUINFOADDR(r3)
	blr


/*
 *  Get value from cputype register
 */
	.text
	.globl	md_cputype
md_cputype:
	mfspr	r3, 287
	blr

/*
 * get/set the L2CR register.
 */

	.globl	md_get_l2cr
md_get_l2cr:
	sync
	isync
	mfspr	r3, L2CR
	sync
	isync
	blr

	.globl	md_set_l2cr
md_set_l2cr:
	sync
	isync
	mtspr	L2CR, r3
	sync
	isync
	blr

/*
 *   cache stuff
 */
        .globl  md_l1_enable
md_l1_enable:
        isync
        or      r4, r3, r3
        mfspr   r3, HID0
        isync
        or      r3, r3, r4
        mtspr   HID0, 3
        isync
        blr

        .globl  md_l1_disable
md_l1_disable:
	isync
	or	r4, r3, r3
	mfspr	r3, HID0
	isync
	andc.	r4, r3, r4
	mtspr	HID0, r4
	isync
	blr

        .globl  md_l2_enable
md_l2_enable:
	isync
	mfspr	r4, L2CR
	or	r3, r4, r3
	isync
	mtspr	L2CR, r3
	isync
	blr

        .globl  md_l2_disable
md_l2_disable:
        isync
        mfspr   r4, L2CR
        andc.	r4, r4, r3
        isync
        mtspr   L2CR, r4
        isync
        blr

/*
 *  Size 750 L2 backside cache. The way to do the sizing is 
 *  to run the L2 cache in test mode, filling it with the line
 *  index, one for each line. The total number of lines with
 *  correct index read back will give the size of the L2 cache.
 */

	.globl	md_size_cache
md_size_cache:

	lis	r3, 0x0020		/* Use memadr @ 2MB */
	li	r4, 0
	lis	r5, 0x0020		/* Max size to scan */

_size_cache_init:
	dcbz	r4, r3			/* Clear cacheline */
	stwx	r4, r4, r3
	dcbf	r4, r3
	addi	r4, r4, 32		/* XXX cache line size */
	cmpw	r4, r5
	bne	_size_cache_init

	li	r4, 0
	li	r7, 0

_size_cache_count:
	lwzx	r6, r4, r3
	cmpw	r6, r4
	bne	_dont_count
	addi	r7, r7, 32
	dcbi	r4, r3			/* invalidate line */
_dont_count:
	addi	r4, r4, 32		/* XXX cacheline */
	cmpw	r4, r5
	bne	_size_cache_count

	or	r3, r7, r7

	blr

/*
 *   Read an address and trap if invalid.
 */
	.globl	md_read_or_trap
md_read_or_trap:
	cmpwi	r4, 0x1
	bne	1f
	lbz	r4, 0(r3)
	b	6f

1:
	cmpwi	r4, 0x2
	bne	2f
	lhz	r4, 0(r3)
	b	6f

2:
	lwz	r4, 0(r3)

6:
	lis	r3, HIADJ(on_acc_data)
	stw	r4, LO(on_acc_data)(r3)
	li	r3, 0

	blr