machdep.c

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	}
	return(1);
}

static void
unpack_fields(hp, vp, reglist, reg)
	char *hp;
	char *vp;
	const struct RegList *reglist;
	register_t reg;
{
	int nl, vl;
	register_t xv;
	const char * const *vs;
	const struct RegMap *regmap;

	hp += sprintf(hp, "          ");
	vp += sprintf(vp, "          ");
	regmap = reglist->regmap;
	while(regmap->width) {
		if(!(regmap->flags & cputype)) {
			regmap++;
			continue;
		}

		xv = (reg >> regmap->bit) & ((1 << regmap->width) -1);
		nl = strlen(regmap->name);
		if(regmap->flags & F_FMT) {
			vl = sprintf(vp, regmap->fe.fmt, 0, xv);
		}
		else {
			vl = nl;
			for(vs = regmap->fe.vn; *vs; vs++) {
				int z = strlen(*vs);
				if(z > vl) {
					vl = z;
				}
			}
		}
		if(vl > nl) nl = vl; else vl = nl; /* Ugly! :) */
		hp += sprintf(hp, " %~*s", nl, regmap->name);
		if(regmap->flags & F_FMT) {
			vp += sprintf(vp, regmap->fe.fmt, vl, xv);
		}
		else {
			vp += sprintf(vp, " %*s", vl, regmap->fe.vn[xv]);
		}
		regmap++;
	}
}

int
md_disp_as_reg(r, c, w)
	register_t *r;
	char *c;
	int *w;
{
	int i;
	char vbuf[100];

	for(i = 0; reglist[i].regoffs >= 0; i++) {
		if(!(reglist->flags & cputype)) {
			continue;
		}
		if(strcasecmp(c, reglist[i].regname) == 0 ||
		   strcasecmp(c, reglist[i].regaltname) == 0) {
			/* Use saved regvalue if value not given */
			register_t regval = *((register_t *)cpuinfotab[whatcpu] + reglist[i].regoffs);
			char *vf;

			if(r != NULL) {
				regval = *r;
			}

			if(matchenv("regsize") == REGSZ_64 &&
			   reglist[i].flags & R_64BIT) {
				vf = "%8s: %016llx ";
			}
			else {
				vf = "%8s: %08x ";
			}
			sprintf(prnbuf, vf, reglist[i].regname, regval);
			(void)more(prnbuf, w, moresz);

			if(reglist[i].regmap) {
				unpack_fields(prnbuf, vbuf, &reglist[i], regval);
				(void)more(prnbuf, w, moresz);
				(void)more(vbuf, w, moresz);
			}
			return(1);
		}
	}
	return(0);
}

const Optdesc md_r_opts[] = {
	{"*", "display all registers"},
	{"r*", "display all general registers"},
	{"f*", "display all fp registers"},
	{"reg value", "set specified register"},
	{0}
};

static void
dsp_rregs(w)
	int *w;
{
	int i;
	char *hp;
	char values[100], *vp;
	char *hf, *vf;

	if(matchenv ("regsize") == REGSZ_64) {
		hf = " %~16s";
		vf = " %016llx";
	}
	else {
		hf = " %~8s";
		vf = " %08x";
	}

	hp = prnbuf;
	vp = values;
	for(i = 0; reglist[i].regoffs >= 0; i++) {
		if(!(reglist[i].flags & R_GPR) || !(reglist[i].flags & cputype)) {
			continue;
		}
		hp += sprintf(hp, hf, reglist[i].regname);
		vp += sprintf(vp, vf,
		    *((register_t *)cpuinfotab[whatcpu] + reglist[i].regoffs));
		if((vp - values) > 65) {
			(void)more(prnbuf, w, moresz);
			sprintf(prnbuf, "%s", values);
			(void)more(prnbuf, w, moresz);
			hp = prnbuf;
			vp = values;
		}
	}
	if(vp > values) {
		(void)more(prnbuf, w, moresz);
		sprintf(prnbuf, "%s", values);
		(void)more(prnbuf, w, moresz);
	}
}

static void
dsp_fregs(w)
	int *w;
{
	int i;
	char *hp;
	char values[100], *vp;
	char *hf, *vf;

	if(matchenv ("fpfmt") == REGSZ_NONE) {
		hf = " %~16s ";
		vf = " %016llx ";

		hp = prnbuf;
		vp = values;
		for(i = 0; reglist[i].regoffs >= 0; i++) {
			if(!(reglist[i].flags & R_FLOAT) || !(reglist[i].flags & cputype)) {
				continue;
			}
			hp += sprintf(hp, hf, reglist[i].regname);
			vp += sprintf(vp, vf,
			    *((register_t *)cpuinfotab[whatcpu] + reglist[i].regoffs));
			if((vp - values) > 65) {
				(void)more(prnbuf, w, moresz);
				sprintf(prnbuf, "%s", values);
				(void)more(prnbuf, w, moresz);
				hp = prnbuf;
				vp = values;
			}
		}
		if(vp > values) {
			(void)more(prnbuf, w, moresz);
			sprintf(prnbuf, "%s", values);
			(void)more(prnbuf, w, moresz);
		}
	}
	else {
		printf("TODO: FP printout in float mode, only 'none' so far!\n");
	}
	sprintf(prnbuf, " ");
	(void)more(prnbuf, w, moresz);
	md_disp_as_reg(NULL, "fsr", w);
}

/*
 *  Machine dependent register display/modify code.
 */
int
md_registers(ac, av)
	int ac;
	char *av[];
{
	register_t *rp;
	register_t rn;
	int w = moresz;

	ioctl (STDIN, CBREAK, NULL);

	switch(ac) {
	case 1: /* No args, display general registers */
		dsp_rregs(&w);
		break;

	case 2:
		if(strcmp(av[1], "*") == 0) {
			dsp_rregs(&w);
			sprintf(prnbuf, " ");
			(void)more(prnbuf, &w, moresz);
			md_disp_as_reg(NULL, "hi", &w);
			md_disp_as_reg(NULL, "lo", &w);
			md_disp_as_reg(NULL, "epc", &w);
			md_disp_as_reg(NULL, "sr", &w);
			md_disp_as_reg(NULL, "cause", &w);
		}
		else if(strcmp(av[1], "r*") == 0) {
			dsp_rregs(&w);
		}
		else if(strcmp(av[1], "f*") == 0) {
			dsp_fregs(&w);
		}
		else {
			if(!md_disp_as_reg(NULL, av[1], &w)) {
				printf("%s: unkown.\n", av[1]);
			}
		}
		break;

	case 3:
		if(md_getregaddr(&rp, av[1]) == 0) {
			printf("%s: unkown.\n", av[1]);
			return(-1);
		}
		if(!get_rsa_reg(&rn, av[2])) {
			return(-1);
		}
		*rp = rn;
		break;
	}

	return(0);
}


/*
 *  Inspect and (future) modify the TLB.
 */
static void
print_tlb(int tlbno, struct tlbdata *tlb)
{
char *attr[] = {
	"CWTNA", "CWTA ", "UCBL ", "CWB  ", "RES  ", "RES  ", "UCNB ", "BPASS"
};

	if(tlb->tlb_lo0 & PG_V || tlb->tlb_lo1 & PG_V) {
		printf("%2d v=0x%08x", tlbno, tlb->tlb_hi & ~0xff);
		printf("/%02x ", tlb->tlb_hi & 0xff);

		if(tlb->tlb_lo0 & PG_V) {
			printf("0x%08x ", pfn_to_pad(tlb->tlb_lo0));
			printf("%c", tlb->tlb_lo0 & PG_M ? 'M' : ' ');
			printf("%c", tlb->tlb_lo0 & PG_G ? 'G' : ' ');
			printf(" %s ", attr[(tlb->tlb_lo0 >> 3) & 7]);
		} else {
			printf("invalid             ");
		}

		if(tlb->tlb_lo1 & PG_V) {
			printf("0x%08x ", pfn_to_pad(tlb->tlb_lo1));
			printf("%c", tlb->tlb_lo1 & PG_M ? 'M' : ' ');
			printf("%c", tlb->tlb_lo1 & PG_G ? 'G' : ' ');
			printf(" %s ", attr[(tlb->tlb_lo1 >> 3) & 7]);
		} else {
			printf("invalid             ");
		}
		printf(" sz=%x", tlb->tlb_mask);
	} else {
		printf("%2d v=invalid    ", tlbno);
	}
	printf("\n");
}

int
md_tlb(int ac, char **av)
{
	struct tlbdata tlb;
	int i;

	switch(ac) {
	case 1: /* No args, display all */
		for (i = 0; i < 64; i++) {
			CPU_GetTLB(i, &tlb);
			print_tlb(i, &tlb);
		}
		break;

	default:
		printf("%s: unkown.\n", av[1]);
		return -1;
		break;
	}
	
	return(0);
}

/*
 *  Cache handling.
 */

void
flushcache()
{
	CPU_FlushCache();
}

void
flushicache(p, s)
	void *p;
	size_t s;
{
	CPU_FlushICache(CACHED_MEMORY_ADDR, CpuPrimaryInstCacheSize);
}

void
flushdcache(p, s)
	void *p;
	size_t s;
{
	CPU_FlushDCache(CACHED_MEMORY_ADDR, CpuPrimaryDataCacheSize);
}

void
syncicache(p, s)
	void *p;
	size_t s;
{
	CPU_FlushDCache((vm_offset_t)p, s);
	CPU_FlushICache((vm_offset_t)p, s);
}

void
flush_cache (type, adr)
     int type;
     void *adr;
{

    switch (type) {
	case ICACHE:
		flushicache((void *)0, (long)memtop);
		break;

	case DCACHE:
		flushdcache((void *)0, (long)memtop);
		break;

	case IADDR:
		syncicache((void *)((int)adr & ~3), 4);
		break;

	case ICACHE|DCACHE:
		flushcache();
		break;
    }
}

/*
 *  Error immune memory read routines.
 */

u_int8_t
load_byte(u_int8_t *adr)
{
	errno = 0;
	if (md_read_or_trap(adr, 1) != 0)
		errno = EPERM;
	return (u_int8_t)on_acc_data;
}

u_int16_t
load_half(u_int16_t *adr)
{
	errno = 0;
	if (md_read_or_trap(adr, 2) != 0)
		errno = EPERM;
	return (u_int16_t)on_acc_data;
}

u_int32_t
load_word(u_int32_t *adr)
{
	errno = 0;
	if (md_read_or_trap(adr, 4) != 0)
		errno = EPERM;
	return (u_int32_t)on_acc_data;
}

u_int64_t
load_dword(u_int64_t *adr)
{
	errno = 0;
	if (md_read_or_trap(adr, 8) != 0)
		errno = EPERM;
	return on_acc_data;
}