start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	dmtc0	a2, COP_0_TLB_PG_MASK   # All pages are 256Mb.

1:
	and	a2, a0, PG_SVPN
	dmtc0   a2, COP_0_TLB_HI	# Set up entry high.

	move	a2, a0
	srl	a2, a0, PG_SHIFT 
	and	a2, a2, PG_FRAME
	ori	a2, PG_IOPAGE
	dmtc0   a2, COP_0_TLB_LO0	# Set up entry low0.
	addu	a2, ((256 * 1024 * 1024) >> PG_SHIFT)
	dmtc0   a2, COP_0_TLB_LO1	# Set up entry low1.

	mtc0    a3, COP_0_TLB_INDEX	# Set the index.
	addiu	a3, 1
	li	a2, (512 * 1024 * 1024)
	subu	a1, a2
	nop
	tlbwi				# Write the TLB

	bgtz	a1, 1b
	addu	a0, a2			# Step address 512Mb.

	mtc0	a3, COP_0_TLB_WIRED	# Set wired to reserved entries.
	jr	ra
	nop
END(CPU_TLBInit)

/*---------------------------------------------------------------------------*/

/*
 *  Set DEVPAR for device bus timing.
 */

	.globl	tgt_setpar125mhz
tgt_setpar125mhz:
	move	a0, ra		/* Don't put in delay slot! */
	bal	do_table	/* Load address to init table */
	nop

	/* Device CS0 - FPGA */
        GTINIT(DEVICE_BANK0PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(7) |	\
				GT_DEVPAR_AccToNext(7)	|	\
				GT_DEVPAR_ALEtoWr(2) |		\
				GT_DEVPAR_WrActive(2) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* Device CS1 - NVRAM */
        GTINIT(DEVICE_BANK1PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(15) |	\
				GT_DEVPAR_AccToNext(15)	|	\
				GT_DEVPAR_ALEtoWr(4) |		\
				GT_DEVPAR_WrActive(8) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* Device CS2 - UART */
        GTINIT(DEVICE_BANK2PARAMETERS, \
				GT_DEVPAR_TurnOff(5) |		\
				GT_DEVPAR_AccToFirst(15) |	\
				GT_DEVPAR_AccToNext(15)	|	\
				GT_DEVPAR_ALEtoWr(6) |		\
				GT_DEVPAR_WrActive(9) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* Device CS3 - Flash Disk */
        GTINIT(DEVICE_BANK3PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(19) |	\
				GT_DEVPAR_AccToNext(19)	|	\
				GT_DEVPAR_ALEtoWr(4) |		\
				GT_DEVPAR_WrActive(8) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* Device BootCS - Boot PROM */
        GTINIT(DEVICE_BOOT_BANK_PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(18) |	\
				GT_DEVPAR_AccToNext(18)	|	\
				GT_DEVPAR_ALEtoWr(4) |		\
				GT_DEVPAR_WrActive(7) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* end mark */
	.word	0, 0

	.globl	tgt_setpar133mhz
tgt_setpar133mhz:
	move	a0, ra		/* Don't put in delay slot! */
	bal	do_table	/* Load address to init table */
	nop

	/* Device CS0 - FPGA */
        GTINIT(DEVICE_BANK0PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(7) |	\
				GT_DEVPAR_AccToNext(7)	|	\
				GT_DEVPAR_ALEtoWr(2) |		\
				GT_DEVPAR_WrActive(2) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* Device CS1 - NVRAM */
        GTINIT(DEVICE_BANK1PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(15) |	\
				GT_DEVPAR_AccToNext(15)	|	\
				GT_DEVPAR_ALEtoWr(4) |		\
				GT_DEVPAR_WrActive(8) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* Device CS2 - UART */
        GTINIT(DEVICE_BANK2PARAMETERS, \
				GT_DEVPAR_TurnOff(5) |		\
				GT_DEVPAR_AccToFirst(15) |	\
				GT_DEVPAR_AccToNext(15)	|	\
				GT_DEVPAR_ALEtoWr(6) |		\
				GT_DEVPAR_WrActive(9) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* Device CS3 - Flash Disk */
        GTINIT(DEVICE_BANK3PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(19) |	\
				GT_DEVPAR_AccToNext(19)	|	\
				GT_DEVPAR_ALEtoWr(4) |		\
				GT_DEVPAR_WrActive(8) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* Device BootCS - Boot PROM */
        GTINIT(DEVICE_BOOT_BANK_PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(18) |	\
				GT_DEVPAR_AccToNext(18)	|	\
				GT_DEVPAR_ALEtoWr(4) |		\
				GT_DEVPAR_WrActive(7) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* end mark */
	.word	0, 0

	.globl	tgt_setpar150mhz
tgt_setpar150mhz:
	move	a0, ra		/* Don't put in delay slot! */
	bal	do_table	/* Load address to init table */
	nop

	/* Device CS0 - FPGA */
        GTINIT(DEVICE_BANK0PARAMETERS, \
				GT_DEVPAR_TurnOff(3) |		\
				GT_DEVPAR_AccToFirst(6) |	\
				GT_DEVPAR_AccToNext(6)	|	\
				GT_DEVPAR_ALEtoWr(3) |		\
				GT_DEVPAR_WrActive(3) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_Reserved)

	/* Device CS1 - NVRAM */
        GTINIT(DEVICE_BANK1PARAMETERS, \
				GT_DEVPAR_TurnOff(3) |		\
				GT_DEVPAR_AccToFirst(10) |	\
				GT_DEVPAR_AccToNext(10)	|	\
				GT_DEVPAR_ALEtoWr(5) |		\
				GT_DEVPAR_WrActive(6) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_Reserved)

	/* Device CS2 - UART */
        GTINIT(DEVICE_BANK2PARAMETERS, \
				GT_DEVPAR_TurnOff(4) |		\
				GT_DEVPAR_AccToFirst(11) |	\
				GT_DEVPAR_AccToNext(11)	|	\
				GT_DEVPAR_ALEtoWr(5) |		\
				GT_DEVPAR_WrActive(6) |		\
				GT_DEVPAR_WrHigh(5) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_Reserved)

	/* Device CS3 - Flash Disk */
        GTINIT(DEVICE_BANK3PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(19) |	\
				GT_DEVPAR_AccToNext(19)	|	\
				GT_DEVPAR_ALEtoWr(4) |		\
				GT_DEVPAR_WrActive(8) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* Device BootCS - Boot PROM */
        GTINIT(DEVICE_BOOT_BANK_PARAMETERS, \
				GT_DEVPAR_TurnOff(2) |		\
				GT_DEVPAR_AccToFirst(19) |	\
				GT_DEVPAR_AccToNext(19)	|	\
				GT_DEVPAR_ALEtoWr(4) |		\
				GT_DEVPAR_WrActive(8) |		\
				GT_DEVPAR_WrHigh(2) |		\
				GT_DEVPAR_DevWidth8 |		\
				GT_DEVPAR_BaddrSkew0 |		\
				GT_DEVPAR_DPEnDisable |		\
				GT_DEVPAR_Reserved)

	/* end mark */
	.word	0, 0

1:
	sw	v1, 0(v0)
do_table:
	lw	v0, 0(ra)		/* Address */
	lw	v1, 4(ra)		/* Data */
	bnez	v0, 1b
	addiu	ra, 8

	jr	a0
	nop


/*
 * Simple character printing routine used before full initialization
 */

LEAF(stringserial)
	move	a2, ra
	addu	a1, a0, s0
	lbu	a0, 0(a1)
1:
	beqz	a0, 2f
	nop
	bal	tgt_putchar
	addiu	a1, 1
	b	1b
	lbu	a0, 0(a1)

2:
	j	a2
	nop
END(stringserial)

LEAF(hexserial)
	move	a2, ra
	move	a1, a0
	li	a3, 7
1:
	rol	a0, a1, 4
	move	a1, a0
	and	a0, 0xf
	la	v0, hexchar
	addu	v0, s0
	addu	v0, a0
	bal	tgt_putchar
	lbu	a0, 0(v0)

	bnez	a3, 1b
	addu	a3, -1

	j	a2
	nop
END(hexserial)
	

LEAF(tgt_putchar)
#if !defined(GTCONSOLE)
	la	v0, COM1_BASE_ADDR
1:
	lbu	v1, NSREG(NS16550_LSR)(v0)
	and	v1, LSR_TXRDY
	beqz	v1, 1b
	nop

	sb	a0, NSREG(NS16550_DATA)(v0)
#else
	la	v0, GT_BASE_ADDR
1:
	lw	v1, CHANNEL0_REGISTER2(v0)
	and	v1, HTOLE32(0x200)
	bnez	v1, 1b
	nop

#if BYTE_ORDER == BIG_ENDIAN
	sll	v1, a0, 24
#endif
	sw	v1, CHANNEL0_REGISTER1(v0)
	lw	v1, CHANNEL0_REGISTER2(v0)
	or	v1, HTOLE32(0x200)
	sw	v1, CHANNEL0_REGISTER2(v0)
#endif
	j	ra
	nop	
END(tgt_putchar)

/* baud rate definition, matchin include/termios.h */
#define B0      0
#define B50     50      
#define B75     75
#define B110    110
#define B134    134
#define B150    150
#define B200    200
#define B300    300
#define B600    600
#define B1200   1200
#define B1800   1800
#define B2400   2400
#define B4800   4800
#define B9600   9600
#define B19200  19200
#define B38400  38400
#define B57600  57600
#define B115200 115200

LEAF(initserial)
#if !defined(GTCONSOLE)
	la	v0, COM1_BASE_ADDR
1:
	li	v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
	sb	v1, NSREG(NS16550_FIFO)(v0)
	li	v1, CFCR_DLAB
	sb	v1, NSREG(NS16550_CFCR)(v0)
	li	v1, NS16550HZ/(16*CONS_BAUD)
	sb	v1, NSREG(NS16550_DATA)(v0)
	srl	v1, 8
	sb	v1, NSREG(NS16550_IER)(v0)
	li	v1, CFCR_8BITS
	sb	v1, NSREG(NS16550_CFCR)(v0)
#if 0
	li	v1, MCR_DTR|MCR_RTS
#endif
	sb	v1, NSREG(NS16550_MCR)(v0)
	li	v1, 0x0
	sb	v1, NSREG(NS16550_IER)(v0)

	move	v1, v0
	la	v0, COM2_BASE_ADDR
	bne	v0, v1, 1b
	nop
#else
	/* Go HUNT, do we need this? */
	lw	v0, CHANNEL0_REGISTER2(s2)
	ori	v0, HTOLE32(0x80000000)
	sw	v0, CHANNEL0_REGISTER2(s2)
#endif
	j	ra
	nop
END(initserial)

LEAF(__main)
	j	ra
	nop
END(__main)

LEAF(makele32)
#if BYTE_ORDER == BIG_ENDIAN
	li	v1, 0xff00ff00
	sll	v0, a0, 8
	and	a0, v1
	and	v0, v1
	srl	a0, a0, 8
	or	a0, v0
	sll	v0, a0, 16
	srl	a0, a0, 16
	or	v0, a0
#else
	move	v0, a0
#endif
	jr	ra
	nop
END(makele32)

	.rdata
transmit_pat_msg:
	.asciz	"\r\nInvalid transmit pattern.  Must be DDDD or DDxDDx\r\n"
v200_msg:
	.asciz	"\r\nPANIC! Unexpected TLB refill exception!\r\n"
v280_msg:
	.asciz	"\r\nPANIC! Unexpected XTLB refill exception!\r\n"
v380_msg:
	.asciz	"\r\nPANIC! Unexpected General exception!\r\n"
v400_msg:
	.asciz	"\r\nPANIC! Unexpected Interrupt exception!\r\n"
hexchar:
	.ascii	"0123456789abcdef"


	.text
	.align	2

/*
 *   I2C Functions used in early startup code to get SPD info from
 *   SDRAM modules. This code must be entirely PIC and RAM independent.
 */

/* Delay macro */
#define	DELAY(count)	\
	li v0, count;	\
99:			\
	bnz	v0, 99b;\
	addiu	v0, -1

#define GT_REGAD(offs)			\
	la	v1, GT_BASE_ADDR+(offs)

#define GT_REGRD(offs)			\
	lw	v0, GT_BASE_ADDR+(offs)

#define GT_REGWR(offs, value)		\
	li	v0, HTOLE32(value);	\
	sw	v0, GT_BASE_ADDR+(offs)

#define GT_REGSET(offs, value)		\
	lw	v0, GT_BASE_ADDR+(offs);\
	li	v1, HTOLE32(value);	\
	or	v0, v1;			\
	sw	v0, GT_BASE_ADDR+(offs)

#define GT_REGCLR(offs, value)		\
	lw	v0, GT_BASE_ADDR+(offs);\
	li	v1, HTOLE32(~(value));	\
	and	v0, v1;			\
	sw	v0, GT_BASE_ADDR+(offs)

#define I2C_INT_ENABLE	0x80
#define I2C_ENABLE	0x40
#define I2C_ACK		0x04
#define I2C_INT_FLAG	0x08
#define I2C_STOP_BIT	0x10
#define I2C_START_BIT	0x20

#define	I2C_AMOD_RD	0x01

#define	BUS_ERROR				0x00
#define	START_CONDITION_TRA			0x08
#define	RSTART_CONDITION_TRA			0x10
#define	ADDR_AND_WRITE_BIT_TRA_ACK_REC		0x18
#define	ADDR_AND_READ_BIT_TRA_ACK_REC		0x40
#define	SLAVE_REC_WRITE_DATA_ACK_TRA		0x28
#define	MAS_REC_READ_DATA_ACK_NOT_TRA		0x58

/*
 *  Wait for interrupt, return status byte
 */
wait_int:
	GT_REGRD(I2C_CONTROL)
	li	v1, HTOLE32(I2C_INT_FLAG)
	and	v0, v1
	beqz	v0, wait_int
	nop

	GT_REGRD(I2C_STATUS_BAUDE_RATE)
	jr	ra
	nop

/*
 *  I2C Master init.
 */

	.globl	boot_i2c_init
boot_i2c_init:

	GT_REGWR(I2C_SOFT_RESET, 0x0)
	GT_REGWR(I2C_STATUS_BAUDE_RATE, 0x24)
	GT_REGWR(I2C_CONTROL, I2C_ENABLE)

	jr	ra
	nop

/*
 * I2C Read byte from device. Use RANDOM READ protocol.
 */

	.globl	boot_i2c_read
boot_i2c_read:

	move	a3, ra				/* Save return address */

	GT_REGSET(I2C_CONTROL, I2C_START_BIT)

	bal	wait_int
	nop

	li	v1, HTOLE32(START_CONDITION_TRA)
	bne	v0, v1, boot_i2c_read_bad		/* Bad start, exit */
	nop
/**/
	andi	v0, a0, 0x700			/* Get device part of addr */
	srl	v0, v0, 7
	ori	v0, 0xa0			/* Device type + write(addr) */
#if BYTE_ORDER == BIG_ENDIAN
	sll	v0, v0, 24
#endif
	GT_REGAD(I2C_DATA)			/* Send device address */
	sw	v0, 0(v1)

	GT_REGCLR(I2C_CONTROL, I2C_INT_FLAG)	/* Send it */

	bal	wait_int
	nop

	li	v1, HTOLE32(ADDR_AND_WRITE_BIT_TRA_ACK_REC)
	bne	v0, v1, boot_i2c_read_bad
	nop
/**/
	andi	v0, a0, 0xff
#if BYTE_ORDER == BIG_ENDIAN
	sll	v0, v0, 24
#endif
	GT_REGAD(I2C_DATA)			/* Send address */
	sw	v0, 0(v1)
	
	GT_REGCLR(I2C_CONTROL, I2C_INT_FLAG)	/* Send it */

	bal	wait_int
	nop

	li	v1, HTOLE32(SLAVE_REC_WRITE_DATA_ACK_TRA)
	bne	v0, v1, boot_i2c_read_bad
	nop
/**/
	GT_REGSET(I2C_CONTROL, I2C_START_BIT)	/* Restart! */
	GT_REGCLR(I2C_CONTROL, I2C_INT_FLAG)	/* Send it */

	bal	wait_int
	nop

	li	v1, HTOLE32(RSTART_CONDITION_TRA)
	bne	v0, v1, boot_i2c_read_bad		/* Bad start, exit */
	nop
/**/
	andi	v0, a0, 0x700			/* Get device part of addr */
	srl	v0, v0, 7
	ori	v0, 0xa1			/* Device type + read */
#if BYTE_ORDER == BIG_ENDIAN
	sll	v0, v0, 24
#endif
	GT_REGAD(I2C_DATA)			/* Send device address */
	sw	v0, 0(v1)

	GT_REGCLR(I2C_CONTROL, I2C_INT_FLAG)	/* Send it */

	bal	wait_int
	nop

	li	v1, HTOLE32(ADDR_AND_READ_BIT_TRA_ACK_REC)
	bne	v0, v1, boot_i2c_read_bad
	nop
/**/
	GT_REGCLR(I2C_CONTROL, I2C_INT_FLAG | I2C_ACK)	/* Get data */
/**/
	bal	wait_int
	nop

	li	v1, HTOLE32(MAS_REC_READ_DATA_ACK_NOT_TRA)
	bne	v1, v0, boot_i2c_read_bad
	nop

	GT_REGRD(I2C_DATA)
#if BYTE_ORDER == BIG_ENDIAN
	srl	v0, v0, 24
#endif

	b	boot_i2c_read_end
	nop
/**/
boot_i2c_read_bad:
	li	v0, -1

boot_i2c_read_end:
	move	a0, v0
	GT_REGSET(I2C_CONTROL, I2C_STOP_BIT)
	GT_REGCLR(I2C_CONTROL, I2C_INT_FLAG)
	move	v0, a0

	jr	a3
	nop

/*
 *  Probe the size of a module.
 */

probe_sdram_size:
	move	t1, ra
	and	t2, a0, 0x0700
	bal	boot_i2c_read
	ori	a0, t2, 5

	bltz	v0, probe_sdram_err	/* Empty slot? */
	move	t3, v0

	bal	boot_i2c_read
	ori	a0, t2, 31

	mult	t3, v0
	bal	boot_i2c_read
	ori	a0, t2, 17

	mflo	t3
	mult	t3, v0
	mflo	v0
	sll	v0, 20

probe_sdram_err:
	jr	t1
	nop