start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	/* Now set up for executing from packet ram. Set up so that
	 * when we return we go to the code copied down to SDRAM
	 * but still in uncached mode. Then we finish setup.
	 */
	la	ra, 3f
	or	ra, UNCACHED_MEMORY_ADDR
	la	v0, PHYS_TO_UNCACHED(PKT_SRAM_BASE)
	jr	v0			/* Execute holding code in packet ram */
	nop

3:
	la	v0, GT_BASE_ADDR+GPP_VALUE
	sw	zero, 0(v0)

	bal	init_caches
	nop

	la	v0, GT_BASE_ADDR+GPP_VALUE
	li	v1, 0x06
	sw	v1, 0(v0)

	la	v0, initmipssmp
	jr	v0
	nop

/*
 *  Return pointer to this cpus info area.
 */
LEAF(md_getcpuinfoptr)
	mfc0	v1, COP_0_PRID
	srl	v1, 24
	andi	v1, 0x07
	la	v0, stack - 16384
	beqz	v1, 1f
	nop
	la	v0, stack - 32768
1:
	jr	ra
	nop
END(md_getcpuinfoptr)

/*
 *  Get the currnet executing CPU save area into k0. May *only* use k0.
 */
LEAF(md_k0_getcputrapsp)
	mfc0	k0, COP_0_PRID
	srl	k0, 24
	andi	k0, 0x07
	beqz	k0, 1f
	la	k0, stack - 16384 -1024
	jr	ra
	nop
1:
	la	k0, stack - 1024
	jr	ra
	nop
END(md_k0_getcputrapsp)



/*
 *  Problem diagnostic dump.
 */
stuck:
#ifdef DEBUG_LOCORE
	TTYDBG("Dumping MV-64340 setup.\r\n")
	TTYDBG("offset----data------------------------.\r\n")
	li	s3, 0
1:
	move	a0, s3
	bal	hexserial
	nop
	TTYDBG(": ")
2:
	add	a0, s3, s2
	lw	a0, 0(a0)
	bal	hexserial
	addiu	s3, 4
	TTYDBG(" ")
	li	a0, 0xfff
	and	a0, s3
	beqz	a0, 3f
	li	a0, 0x01f
	and	a0, s3
	bnez	a0, 2b
	TTYDBG("\r\n")
	b	1b
	nop
3:
	b	3b
	nop

#else
	b	stuck
	nop
#endif

/*
 *  Reset and initialize caches to a known state.
 */
#define IndexStoreTagI	0x08
#define IndexStoreTagD	0x09
#define IndexStoreTagS	0x0b
#define FillI		0x14

/*
 *  RM7000 config register bits.
 */
#define CF_7_SE         (1 << 3)        /* Secondary cache enable */
#define CF_7_SC         (1 << 31)       /* Secondary cache not present */
#define CF_7_TE         (1 << 12)       /* Tertiary cache enable */
#define CF_7_TC         (1 << 17)       /* Tertiary cache not present */
#define CF_7_TS         (3 << 20)       /* Tertiary cache size */
#define CF_7_TS_AL      20              /* Shift to align */
#define NOP8 nop;nop;nop;nop;nop;nop;nop;nop

LEAF(init_caches)
	mfc0	t3, COP_0_CONFIG	/* t3 = original config */
	and	t3, 0xffffeff8		/* Make sure coherency is OK */
#if !defined(XXXSMP)
	or	t3, 0x3
#else
	or	t3, 0x5			/* Does not work on 1.x silicon */
#endif
	li	t2, 4096		/* this is 2^12 for cache calculation */

	srl	t1, t3, 9
	and	t1, 7
	sllv	t5, t2, t1		/* t5 = I cache size */

	and	t1, t3, 0x20
	srl	t1, t1, 1
	addu	t6, t1, 16		/* t6 = I cache line size */

	srl	t1, t3, 6
	and	t1, 7
	sllv	t7, t2, t1		/* t7 = D cache size */

	and	t1, t3, 0x10
	addu	t8, t1, 16		/* t8 = D cache line size */

Conf7KL2:
	and	t1, t3, CF_7_SC
	bnez	t1, Conf7KEnd
	li	t9, 0

	li	t9, 0x40000		/* Size of L2 cache = 256KB */
	or	t3, t3, CF_7_SE		/* Enable L2 if present */

Conf7KEnd:

	mfc0	t0, COP_0_STATUS_REG
	and	t1, t0, SR_BOOT_EXC_VEC
	or	t1, SR_DIAG_DE
	mtc0	t1, COP_0_STATUS_REG

	mtc0	zero, COP_0_TAG_LO
	mtc0	zero, COP_0_TAG_LO,1	/* DataLo */
	mtc0	zero, COP_0_TAG_LO,3	/* DataX  */
	mtc0	zero, COP_0_TAG_HI
	mtc0	zero, COP_0_TAG_HI,1	/* DataHi */
	mtc0	zero, COP_0_ECC

	/* Disable L2 */
	and	t3, t3, ~(CF_7_SE)
	mtc0	t3, COP_0_CONFIG
	NOP8

/*
 *  Do L1 instruction cache.
 */

	la	a0, 0x80000000
	addu	a1, a0, t5			/* how large is the I-cache */
1:
	cache	IndexStoreTagI, 0(a0)		/* clear tag */
	cache	IndexStoreTagI, 8(a0)		/* clear tag */
	cache	IndexStoreTagI, 16(a0)		/* clear tag */
	cache	IndexStoreTagI, 24(a0)		/* clear tag */
	addu	a0, t6				/* count by lines */
	bne	a0, a1, 1b
	nop

/*
 *  Do L1 data cache.
 */

	la	a0, 0x80000000
	addu	a1, a0, t7			/* how large is the D-cache */
1:
	cache	IndexStoreTagD, 0(a0)		/* clear tag */
	cache	IndexStoreTagD, 8(a0)		/* clear tag */
	cache	IndexStoreTagD, 16(a0)		/* clear tag */
	cache	IndexStoreTagD, 24(a0)		/* clear tag */
	addu	a0, t8				/* count by lines */
	bne	a0, a1, 1b
	nop

	beqz	t9, no_L2_cache
	nop

/*
 *  Do L2 cache
 */

	/* Enable L2 */
	or	t3, t3, CF_7_SE
	mtc0	t3, COP_0_CONFIG
	NOP8

	la	a0, 0x80000000
	addu	a1, a0, 256*1024		/* find the end */
1:
	cache	IndexStoreTagS, 0(a0)		/* init tag */
	cache	IndexStoreTagS, 8(a0)		/* init tag */
	cache	IndexStoreTagS, 16(a0)		/* init tag */
	cache	IndexStoreTagS, 24(a0)		/* init tag */
	addu	a0, 0x20			/* advance by linesz */
	bne	a0, a1, 1b
	nop

no_L2_cache:

	mfc0	t0, COP_0_STATUS_REG
	NOP8
	and	t0, ~(SR_DIAG_DE)
	mtc0	t0, COP_0_STATUS_REG		/* Restore status reg */
	NOP8
	jr	ra
	nop
END(init_caches)

/*---------------------------------------------------------------------------*/

/*
 * Set up SDRAM on the Gemeni. Various models depending on
 * processor version and user jumper.
 */
LEAF(init_gemini_sdram)
	move	t9, ra

	bal	probe_sdram_size
	li	a0, 0x000

	bltz	v0, gem_no_mem
	nop

	bal	boot_i2c_read		/* Get number of rows from primary */
	li	a0, 0x003

	li	v1, 12
	beq	v0, v1, m0init_16x8
	li	v1, 13
	bne	v0, v1, gem_no_mem
	nop

m0init_32x8:
	TTYDBG("Using 32x8 Configuration\r\n")

	la	v0, FPGA_BASE_ADDR
	lb	t0, BOARD_STAT(v0)
	and	t0, 0x80
	bnez	t0, gem_no_mem
	nop
	bal	doinit
	nop

	RM9K_INIT(0x300, 0x000302d9)
	RM9K_INIT(0x108, 0x00000001)	/* LKB1 */
	RM9K_INIT(0x10c, 0x00ffff00)
	RM9K_INIT(0x344, 0x022f9481)
	RM9K_INIT(0x340, 0x00004025)
	RM9K_INIT(0x304, 0x00000000)	/* Rank 0 */

	/* RM9k errata -- must set to CL3 to get 2.5 */
	RM9K_INIT(0x344, 0x022f9482)
	.word 0, 0

m0init_16x8:
	TTYDBG("Using 16x8 Configuration\r\n")

	la	v0, FPGA_BASE_ADDR
	lb	t0, BOARD_STAT(v0)
	and	t0, 0x80
	bnez	t0, m0init_16x8_swap
	nop
	bal	doinit
	nop

	RM9K_INIT(0x300, 0x000302d9)
	RM9K_INIT(0x108, 0x00000001)	/* LKB1 */
	RM9K_INIT(0x10c, 0x007fff00)
	RM9K_INIT(0x110, 0x00800001)	/* LKB2 */
	RM9K_INIT(0x114, 0x007fff00)
	RM9K_INIT(0x344, 0x022f9481)
	RM9K_INIT(0x354, 0x022f9481)
	RM9K_INIT(0x340, 0x00004015)
	RM9K_INIT(0x350, 0x00004015)
	RM9K_INIT(0x304, 0x00000000)	/* Rank 0 */
	RM9K_INIT(0x304, 0x00000001)	/* Rank 1 */

	/* RM9k errata -- must set to CL3 to get 2.5 */
	RM9K_INIT(0x344, 0x022f9482)
	RM9K_INIT(0x354, 0x022f9482)
	.word 0, 0

m0init_16x8_swap:
	bal	doinit
	nop

	RM9K_INIT(0x300, 0x000302d9)
	RM9K_INIT(0x108, 0x00800001)	/* LKB1 */
	RM9K_INIT(0x10c, 0x007fff00)
	RM9K_INIT(0x110, 0x01000001)	/* LKB2 */
	RM9K_INIT(0x114, 0x007fff00)
	RM9K_INIT(0x344, 0x022f9481)
	RM9K_INIT(0x354, 0x022f9481)
	RM9K_INIT(0x340, 0x00004015)
	RM9K_INIT(0x350, 0x00004015)
	RM9K_INIT(0x304, 0x00000000)	/* Rank 0 */
	RM9K_INIT(0x304, 0x00000001)	/* Rank 1 */

	/* RM9k errata -- must set to CL3 to get 2.5 */
	RM9K_INIT(0x344, 0x022f9482)
	RM9K_INIT(0x354, 0x022f9482)
	.word 0, 0

doinit:
	b	2f
	nop

1:
	sw	v1, 0(v0)
2:
	lw	v0, 0(ra)		/* Address */
	lw	v1, 4(ra)		/* Data */
	bnez	v0, 1b
	addiu	ra, 8

	li	s4, 0x10000000		/* XXX Should be real size */

gem_no_mem:
	jr	t9
	nop
END(init_gemini_sdram)


/*
 *  Set up any modules on the MV64340. This code assumes
 *  both modules to be the same size and type. Either
 *  slot may be fitted. We use parameters from first found.
 */
LEAF(init_mv64340_sdram)
	move	t9, ra
	TTYDBG("SDRAM Setting up MV64340\r\n")

	/* Disable LK6 in case there are no memory on the GT64340 */
	la	v0, RM9K_BASE_ADDR
	sw	zero, 0x130(v0)
	lw	t0, 0x130(v0)

	bal	probe_sdram_size
	li	a0, 0x200
	bgtz	v0, 1f
	nop
	bal	probe_sdram_size
	li	a0, 0x300
	bltz	v0, mv_no_modules
	nop

1:
	/* set LKM6 for 128MByte */
	la	v0, RM9K_BASE_ADDR
	li	t0, 0x007fff00
	sw	t0, 0x134(v0)
	lw	t0, 0x134(v0)
	sync

	/* set LKB6 for 0x0000_0000 base */
	srl	t0, s4, 4
	ori	t0, 0x00000001
	sw	t0, 0x130(v0)
	lw	t0, 0x130(v0)
	sync

	bal	makele32
	srl	a0, s4, 16
	sw	v0, SCS_0_BASE_ADDRESS(s2)
	li	v0, HTOLE32(0x07ff)
	sw	v0, SCS_0_SIZE(s2)		/* Map 128Mb */

	lw	v0, CPU_BASE_ADDRESS_ENABLE(s2)
	and	v0, HTOLE32(0xfffffff0)
	or	v0, HTOLE32(0x0000000e)
	sw	v0, CPU_BASE_ADDRESS_ENABLE(s2)

	li	s5, 0x08000000		/* XXX Should use real size! */

	bal	boot_i2c_read		/* Get module type from primary */
	li	a0, 0x215
	move	t0, v0
	bal	boot_i2c_read		/* Address size */
	li	a0, 0x203
	move	t1, v0
	bal	boot_i2c_read		/* Latency */
	li	a0, 0x212

	b	mv_init_dll
	move	t2, v0

	bal	boot_i2c_read		/* Get module type from secondary */
	li	a0, 0x315

	move	t0, v0
	bal	boot_i2c_read		/* Address size */
	li	a0, 0x303
	move	t1, v0
	bal	boot_i2c_read		/* Latency */
	li	a0, 0x312
	move	t2, v0

/*
 * DDL Initializations (133Mhz)
 */
mv_init_dll:
	sw	zero, SRAM_ADDRESS(s2)
	bal	1f
	li	v0, 64

	.word HTOLE32(0x00000000), HTOLE32(0x00000041), HTOLE32(0x00000082)
	.word HTOLE32(0x000000c3), HTOLE32(0x00000104), HTOLE32(0x00000145)
	.word HTOLE32(0x00000186), HTOLE32(0x000001c7), HTOLE32(0x00000208)
	.word HTOLE32(0x00000249), HTOLE32(0x0000028a), HTOLE32(0x000002cb)
	.word HTOLE32(0x0000030c), HTOLE32(0x0000034d), HTOLE32(0x0000038e)
	.word HTOLE32(0x000003cf), HTOLE32(0x00000410), HTOLE32(0x00000451)
	.word HTOLE32(0x00000492), HTOLE32(0x000004d3), HTOLE32(0x00000514)
	.word HTOLE32(0x00000555), HTOLE32(0x00000596), HTOLE32(0x000005d7)
	.word HTOLE32(0x00000618), HTOLE32(0x00000659), HTOLE32(0x0000069a)
	.word HTOLE32(0x000006db), HTOLE32(0x0000071c), HTOLE32(0x0000075d)
	.word HTOLE32(0x0000079e), HTOLE32(0x000007df), HTOLE32(0x00000820)
	.word HTOLE32(0x00000861), HTOLE32(0x000008a2), HTOLE32(0x000008e3)
	.word HTOLE32(0x00000924), HTOLE32(0x00000965), HTOLE32(0x000009a6)
	.word HTOLE32(0x000009e7), HTOLE32(0x00000a28), HTOLE32(0x00000a69)
	.word HTOLE32(0x00000aaa), HTOLE32(0x00000aeb), HTOLE32(0x00000b2c)
	.word HTOLE32(0x00000b6d), HTOLE32(0x00000bae), HTOLE32(0x00000bef)
	.word HTOLE32(0x00000c30), HTOLE32(0x00000c71), HTOLE32(0x00000cb2)
	.word HTOLE32(0x00000cf3), HTOLE32(0x00000d34), HTOLE32(0x00000d75)
	.word HTOLE32(0x00000db6), HTOLE32(0x00000df7), HTOLE32(0x00000e38)
	.word HTOLE32(0x00000e79), HTOLE32(0x00000eba), HTOLE32(0x00000efb)
	.word HTOLE32(0x00000f3c), HTOLE32(0x00000f7d), HTOLE32(0x00000fbe)
	.word HTOLE32(0x00000fff)

1:
	lw	v1, 0(ra)		/* Data */
	sw	v1, SRAM_DATA0(s2)
	addiu	v0, -1
	bnez	v0, 1b
	addiu	ra, 4

	li	v0, HTOLE32(0x00300000)
	sw	v0, DFCDL_CONFIGURATION0(s2)

	/* Send a NOP */
	li	v0, HTOLE32(0x00000005)
	sw	v0, SDRAM_OPERATION(s2)
	lw	v0, SDRAM_OPERATION(s2)		/* this flushes the store */
	li	v0, HTOLE32(0x00000007)
1:
	lw	v1, SDRAM_OPERATION(s2)
	and	v1, v0
	bnez	v1, 1b
	nop

/*
 *  Configure for registred or non registred modules.
 */
	andi	t0, 0x02
	beqz	t0, mv_sdram_nonreg
	nop

	TTYDBG("SDRAM registred\r\n")
	li	v0, HTOLE32(0x58220400)
	b	mv_sdram_config
	nop

mv_sdram_nonreg:
	TTYDBG("SDRAM non-registred\r\n")
	li	v0, HTOLE32(0x58200400)

mv_sdram_config:
	sw	v0, SDRAM_CONFIGURATION(s2)
	sw	zero, SDRAM_OPEN_PAGES_CONTROL(s2)
	
/*
 *  Select CAS latency.
 */
	lw	t4, DUNIT_CONTROL_LOW(s2)
	and	t4, HTOLE32(0x00000001)
/*
 *  Now t0 = 0 if non-reg, t4 = 0 if clocks are synchronized in Dunit.
 */

	srl	t2, 2
	li	t3, HTOLE32(0x00000052)
	beqz	t2, mv_cas_mode
	li	v0, 0			# 1.5
	srl	t2, 1
	li	t3, HTOLE32(0x00000022)
	beqz	t2, mv_cas_mode
	li	v0, 16			# 2.0
	srl	t2, 1
	li	t3, HTOLE32(0x00000062)
	beqz	t2, mv_cas_mode
	li	v0, 32			# 2.5

	li	t3, HTOLE32(0x00000032)
	li	v0, 48			# 3.0

mv_cas_mode:
	bnez	t4, 1f
	nop
	ori	v0, 8
1:
	bnez	t0, 2f
	nop
	ori	v0, 4
2:
	bal	mv_setcas
	nop

/*  Table for different cas latency settings.
 *  Values are in order StBurstDelay for
 *  Sync/Reg, Sync/Non-Reg, Async/Reg, Async/NonReg
 */
/* Cas 1.5 */	.word	HTOLE32(0x24110000), HTOLE32(0x23110000)
		.word	HTOLE32(0x0b110000), HTOLE32(0x1a110780)
/* Cas 2.0 */	.word	HTOLE32(0x04110000), HTOLE32(0x03110000)
		.word	HTOLE32(0x3c110000), HTOLE32(0x3b110780)
/* Cas 2.5 */	.word	HTOLE32(0x25110000), HTOLE32(0x24110000)
		.word	HTOLE32(0x0c110000), HTOLE32(0x1b110780)
/* Cas 3.0 */	.word	HTOLE32(0x05110000), HTOLE32(0x04110000)
		.word	HTOLE32(0x3d110000), HTOLE32(0x3c110780)
/* Cas 3.5 */	.word	HTOLE32(0x26110000), HTOLE32(0x25110000)
		.word	HTOLE32(0x0d110000), HTOLE32(0x1c110780)
/* Cas 4.0 */	.word	HTOLE32(0x06110000), HTOLE32(0x05110000)
		.word	HTOLE32(0x3d110000), HTOLE32(0x3e110780)

mv_setcas:
	/* issue Mode Register Set command */
	li	t0, HTOLE32(0x00000003)
	sw	t0, SDRAM_OPERATION(s2)
	lw	t0, SDRAM_OPERATION(s2)		/* this flushes the store */
	li	t0, HTOLE32(0x00000007)
1:
	lw	v1, SDRAM_OPERATION(s2)
	and	v1, t0
	bnez	v1, 1b
	nop

	addu	v1, v0, ra
	lw	v1, 0(v1)
	lw	t0, DUNIT_CONTROL_LOW(s2)
	and	t0, HTOLE32(0x0000007f)
	or	t0, v1
	sw	t0, DUNIT_CONTROL_LOW(s2)
	TTYDBG("SDRAM Cas settings: ")
	TTYDBGHEX(t0)
	TTYDBG("\r\n")

	sw	t3, SDRAM_MODE(s2)

	/* issue Mode Register Set command */
	li	t0, HTOLE32(0x00000003)
	sw	t0, SDRAM_OPERATION(s2)
	lw	t0, SDRAM_OPERATION(s2)		/* this flushes the store */
	li	t0, HTOLE32(0x00000007)
1:
	lw	v1, SDRAM_OPERATION(s2)
	and	v1, t0
	bnez	v1, 1b
	nop

/*
 *  XXX, This needs more combinations.
 */
	li	v1, HTOLE32(0x00000002)
	li	t0, 12
	beq	t0, t1, mv_setdens
	nop

	li	v1, HTOLE32(0x00000012)
	li	t0, 13
	beq	t0, t1, mv_setdens
	nop

	li	v1, HTOLE32(0x00000022)

mv_setdens:
	sw	v1, SDRAM_ADDRESS_CONTROL(s2)

	li	v1, HTOLE32(0x11511220)
	b	mv_mem_done
	sw	v1, SDRAM_TIMING_LOW(s2)

mv_no_modules:
	TTYDBG("SDRAM Slot 1 empty.\r\n")
	PRINTSTR("WARN: No PCI DMA memory. PCI devices may not work!\r\n")

mv_mem_done:
	jr	t9
	nop
END(init_mv64340_sdram)

/*---------------------------------------------------------------------------*/

/*
 *  Clear the TLB. Normally called from start.S.
 */
LEAF(CPU_TLBClear)
	li	a3, 0			# First TLB index.

	li	a2, PG_SIZE_4K
	dmtc0   a2, COP_0_TLB_PG_MASK   # Whatever...

1:
	dmtc0   zero, COP_0_TLB_HI	# Clear entry high.
	dmtc0   zero, COP_0_TLB_LO0	# Clear entry low0.
	dmtc0   zero, COP_0_TLB_LO1	# Clear entry low1.

	mtc0    a3, COP_0_TLB_INDEX	# Set the index.
	addiu	a3, 1
	li	a2, 64
	nop
	nop
	tlbwi				# Write the TLB

	bne	a3, a2, 1b
	nop

	jr	ra
	nop
END(CPU_TLBClear)

/*
 *  Set up the TLB. Normally called from start.S.
 */
LEAF(CPU_TLBInit)
	li	a3, 0			# First TLB index.

	li	a2, PG_SIZE_256M