pci_machdep.c

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

		stat |= 1 << 6;

		/* write and readback to force a posting */
		RM9K_WRITE(0x6fc, stat);
		stat = RM9K_READ(0x6fc);

		/* set 'transmit off' bit */
		stat |= 1 << 7;

		/* write and readback to force a posting */
		RM9K_WRITE(0x6fc, stat);
		stat = RM9K_READ(0x6fc);
	}
	
        /*
         *  Set up mapping for PCI to localmem accesses.
	 *  config regs to find mapping and size. BAR and
	 *  size register should be set to match SDRAM SCS.
	 *  We use PCI0 I/O and PCI0 MEM0. Same for PCI1.
         */

	stat = GT_READ(CPU_BASE_ADDRESS_ENABLE);
	stat |= (1<<11) | (1<<12) | (1<<13) | (1<<16) | (1<<17) | (1<<18);
	stat &= ~((1<<9) | (1<<10) | (1<<14) | (1<<15));
	GT_WRITE(CPU_BASE_ADDRESS_ENABLE, stat);

	if (hypertransport_enable) {
		RM9K_WRITE(0x610, 6);		/* HTBAR0 */
		RM9K_WRITE(0x688, 0xffff);	/* HTMASK0 */
	}

	for(i = 0; i < NBARS; i++) {
		u_int32_t baselo, basesize;

		baselo = GT_READ(barlist[i].scslow) << 16;
		basesize = (GT_READ(barlist[i].scssize) + 1) << 16;
		basesize = -1;

		/* bus 0 */
		tag = _pci_make_tag(0, 0, (barlist[i].barl & 0x700) >> 8);
		stat = _pci_conf_read(tag, barlist[i].barl & 0xff) & 0xffff;
		stat |= baselo & 0xfffff000;
		_pci_conf_write(tag, barlist[i].barl & 0xff, stat);
		_pci_conf_write(tag, barlist[i].barh & 0xff, 0);

		/* bus 1 */
		tag = _pci_make_tag(1, 0, (barlist[i].barl & 0x700) >> 8);
		stat = _pci_conf_read(tag, barlist[i].barl & 0xff) & 0xffff;
		stat |= baselo & 0xfffff000;
		_pci_conf_write(tag, barlist[i].barl & 0xff, stat);
		_pci_conf_write(tag, barlist[i].barh & 0xff, 0);

		/* set size registers */
		GT_WRITE(barlist[i].pci0size, basesize & 0xfffff000);
		GT_WRITE(barlist[i].pci1size, basesize & 0xfffff000);
	}

	/* Configure the Internal Registers decode space */
	/* bus 0 */
	tag = _pci_make_tag(0, 0, 0);
	stat = _pci_conf_read(tag,
		PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS) & 0xffff;
	stat |= GT_BASE_ADDR & 0xfffff000;
	_pci_conf_write(tag,
		PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, stat);

	/* bus 1 */
	tag = _pci_make_tag(1, 0, 0);
	stat = _pci_conf_read(tag,
		PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS) & 0xffff;
	stat |= GT_BASE_ADDR & 0xfffff000;
	_pci_conf_write(tag,
		PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, stat);

	/* enable the PCI slave windows we want */
	stat = GT_READ(PCI_0BASE_ADDRESS_REGISTERS_ENABLE);
	stat |= GT_READ(CPU_BASE_ADDRESS_ENABLE) & 0x07ff;
	GT_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, stat);
	stat = GT_READ(PCI_1BASE_ADDRESS_REGISTERS_ENABLE);
	stat |= GT_READ(CPU_BASE_ADDRESS_ENABLE) & 0x07ff;
	GT_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, stat);

	return(3);
}


/*
 * Called to reinitialise the bridge after we've scanned each PCI device
 * and know what is possible. We also set up the interrupt controller
 * routing and level control registers.
 */
void
_pci_hwreinit (void)
{
}

void
_pci_flush (void)
{
}


/*
 *  Map the CPU virtual address of an area of local memory to a PCI
 *  address that can be used by a PCI bus master to access it.
 */
vm_offset_t
_pci_dmamap(va, len)
	vm_offset_t va;
	unsigned int len;
{
	return(pci_local_mem_pci_base + VA_TO_PA (va));
}

/*
 *  Map the PCI address of an area of local memory to a CPU physical
 *  address.
 */
vm_offset_t
_pci_cpumap(pcia, len)
	vm_offset_t pcia;
	unsigned int len;
{
	return PA_TO_VA(pcia - pci_local_mem_pci_base);
}


/*
 *  Make pci tag from bus, device and function data.
 */
pcitag_t
_pci_make_tag(bus, device, function)
	int bus;
	int device;
	int function;
{
	pcitag_t tag;

	tag = (bus << 16) | (device << 11) | (function << 8);
	return(tag);
}

/*
 *  Break up a pci tag to bus, device function components.
 */
void
_pci_break_tag(tag, busp, devicep, functionp)
	pcitag_t tag;
	int *busp;
	int *devicep;
	int *functionp;
{
	if (busp) {
		*busp = (tag >> 16) & 255;
	}
	if (devicep) {
		*devicep = (tag >> 11) & 31;
	}
	if (functionp) {
		*functionp = (tag >> 8) & 7;
	}
}

int
_pci_canscan (pcitag_t tag)
{
	int bus, device, function;

	_pci_break_tag (tag, &bus, &device, &function); 
	if(device == 0) {
		return(0);	/* Ignore the Discovery and HT host itself */
	}
	return (1);
}

/*
 *  Read a value form PCI configuration space. Support for
 *  all three data sizes (byte, halfword and word) is provided.
 */
static pcireg_t
_pci_conf_readn(tag, reg, width)
	pcitag_t tag;
	int reg;
	int width;
{
	pcireg_t data;
	u_int32_t adr;
	int bus, device, function;

	if (reg & (width-1) || reg < 0 || reg >= 0x100) {
		if (_pciverbose >= 1) {
			_pci_tagprintf (tag, "_pci_conf_read: bad reg 0x%x\r\n", reg);
		}
		return ~0;
	}

	_pci_break_tag (tag, &bus, &device, &function); 
	/* Type 0 configuration on onboard PCI bus */
	if (device > 29 || function > 7) {
		return ~0;		/* device out of range */
	}
	adr = (bus << 16) | (device << 11) | (function << 8) | reg | GT_IPCI_CFGADDR_ConfigEn;

	if(bus == 0) {
		GT_WRITE(PCI_0CONFIGURATION_ADDRESS, adr);
		data = GT_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER);
	} else if (bus == 1 ) {
		GT_WRITE(PCI_1CONFIGURATION_ADDRESS, adr);
		data = GT_READ(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER);
	} else {
		if (!hypertransport_enable || device != 1)
			return ~0;

		/* HyperTransport */
		/* determine if a Type 1 cycle is needed */
		adr = (device << 11) | (function << 8) | reg | 0x80000000;
		if (bus != 2) {
			adr |= (bus << 16) | 1;
		}
		RM9K_WRITE(0x6f8, adr);
		if (read32_or_trap((int32_t *)(RM9K_BASE_ADDR+0x6fc)))
			data = ~0;
		else
			data = RM9K_READ(0x6fc);
	}

	return data;
}


pcireg_t
_pci_conf_read(pcitag_t tag, int reg)
{
	return _pci_conf_readn(tag, reg, 4);
}

/*
 *  Write a value to PCI configuration space.
 */
static void
_pci_conf_writen(tag, reg, data, width)
	pcitag_t tag;
	int reg;
	pcireg_t data;
	int width;
{
	u_int32_t adr;
	int bus, device, function;

	if (reg & (width-1) || reg < 0 || reg >= 0x100) {
		if (_pciverbose >= 1) { 
			_pci_tagprintf(tag, "_pci_conf_write: bad reg 0x%x\r\n", reg);
		}
		return;
	}

	_pci_break_tag (tag, &bus, &device, &function);

	/* Type 0 configuration on onboard PCI buses */
	if (device > 29 || function > 7) {
		return;		/* device out of range */
	}
	adr = (bus << 16) | (device << 11) | (function << 8) | reg | GT_IPCI_CFGADDR_ConfigEn;

	if(bus == 0) {
		GT_WRITE(PCI_0CONFIGURATION_ADDRESS, adr);
		GT_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, data);
	} else if (bus == 1) {
		GT_WRITE(PCI_1CONFIGURATION_ADDRESS, adr);
		GT_WRITE(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, data);
	} else {
		if (!hypertransport_enable)
			return;

		/* HyperTransport */
		/* determine if a Type 1 cycle is needed */
		adr = (device << 11) | (function << 8) | reg | 0x80000000;
		if (bus != 2) {
			adr |= (bus << 16) | 1;
		}
		RM9K_WRITE(0x6f8, adr);
		RM9K_WRITE(0x6fc, data);
	}
}

void
_pci_conf_write(pcitag_t tag, int reg, pcireg_t data)
{
    _pci_conf_writen (tag, reg, data, 4);
}


/*
 *  Get contents of PCI Mapping register and do any machine
 *  dependent mapping setup.
 */
int
_pci_map_port(tag, reg, port)
	pcitag_t tag;
	int reg;
	unsigned int *port;
{
	pcireg_t address;
    
	if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) {
		if (_pciverbose >= 1) {
			_pci_tagprintf(tag, "_pci_map_port: bad request\r\n");
		}
		return -1;
	}
    
	address = _pci_conf_read(tag, reg);
    
	if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) {
		if (_pciverbose >= 1) {
			_pci_tagprintf (tag, "_pci_map_port: attempt to i/o map a memory region\r\n");
		}
		return(-1);
	}

	*port = (address & PCI_MAPREG_IO_ADDR_MASK) - PCI_IO_SPACE_PCI_BASE;
	return(0);
}

void *
_pci_map_int(tag, level, func, arg)
	pcitag_t tag;
	int level;
	int (*func) __P((void *));
	void *arg;
{
	pcireg_t data;
	int pin, bus, device;

	data = _pci_conf_read(tag, PCI_INTERRUPT_REG);

	pin = PCI_INTERRUPT_PIN(data);

	if (pin == 0) {
		/* No IRQ used. */
		return NULL;
	}

	if (pin > 4) {
		if (_pciverbose >= 1) {
			_pci_tagprintf (tag, "_pci_map_int: bad interrupt pin %d\r\n", pin);
		}
		return(NULL);
	}


	_pci_break_tag (tag, &bus, &device, NULL);

	if (bus != 0 || device > 5) {
		return(NULL);
	}

	/* XXX need to work this out based on device number etc. */
	_pci_tagprintf(tag, "_pci_map_int: attempt to map device %d pin %c\n", 
		   device, '@' + pin);
	return(NULL);
}

void
pci_sync_cache(p, adr, size, rw)
	void *p;
	vm_offset_t adr;
	size_t size;
	int rw;
{
	CPU_IOFlushDCache(adr, size, rw);
}