start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

 */
	GT_REGWR(SCS0_LOW, 0xfff)	/* Turn off all decoders first */
        GT_REGWR(SCS0_HIGH, 0x0)
        GT_REGWR(SCS1_LOW, 0xfff)
        GT_REGWR(SCS1_HIGH, 0)
        GT_REGWR(SCS2_LOW, 0xfff)
        GT_REGWR(SCS2_HIGH, 0)
        GT_REGWR(SCS3_LOW, 0xfff)
        GT_REGWR(SCS3_HIGH, 0)

/*  Configure MAIN SDRAM module if poulated */

	cmpwi	r17, 0
	beq	sdram_slot1_config

	DBGPRINTSTR("INIT SDRAM Bank 1\r\n")

	li	r3, 1			/* Get number of module banks */
	cmpwi	r3, 2
	beq	sdram_slot0_2bank

	DBGPRINTSTR("Single bank\r\n")
	GT_REGWR(SCS0_LOW, 0)		/* Module starts at address 0 */
	GT_REGAD(SCS0_HIGH)
	srwi	r6, r17, 20		/* Make end value for GT reg */
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	b	sdram_slot1_config

sdram_slot0_2bank:
	DBGPRINTSTR("Dual bank\r\n")
	GT_REGWR(SCS0_LOW, 0)		/* Module starts at address 0 */
	GT_REGAD(SCS1_LOW)
	srwi	r6, r17, 21
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS0_HIGH)
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS1_HIGH)
	srwi	r6, r17, 20
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 

/*  Configure SECONDARY SDRAM module if poulated */

sdram_slot1_config:

	cmpwi	r18, 0
	beq	sdram_set_param		/* empty */

	DBGPRINTSTR("INIT SDRAM Bank 2\r\n")

	li	r3, 1			/* Get number of module banks */
	cmpwi	r3, 2
	beq	sdram_slot1_2bank

	DBGPRINTSTR("Single bank\r\n")
	GT_REGAD(SCS2_LOW)		/* Module starts at address 0 */
	srwi	r6, r17, 20		/* Make end value for GT reg */
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS2_HIGH)
	add	r6, r17, r18
	srwi	r6, r6, 20		/* Make end value for GT reg */
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	b	sdram_set_param

sdram_slot1_2bank:
	DBGPRINTSTR("Dual bank\r\n")
	GT_REGAD(SCS2_LOW)		/* Module starts at address 0 */
	srwi	r6, r17, 20		/* Make end value for GT reg */
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS3_LOW)
	srwi	r6, r17, 20
	srwi	r4, r18, 21
	add	r6, r6, r4
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS2_HIGH)
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS3_HIGH)
	add	r6, r17, r18
	srwi	r6, r6, 20		/* Make end value for GT reg */
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 

sdram_set_param:

/* Init parameters. Both banks assumed to be the same. */

	lis	r5, HIADJ(MISC_MBSZ)
	lbz	r4, LO(MISC_MBSZ)(r5)
	andi.	r4, r4, 7

	lis	r6, 0x000f		/* Keep pages open */
	ori	r6, r6, 0x8000
	cmpwi	r4, 0x0			/* 64 MB */
	beq	sdram_set_density
	cmpwi	r4, 0x1			/* 128 MB */
	beq	sdram_set_density
	ori	r6, r6, 0xc000		/* 256 MB or 512 MB */

sdram_set_density:
        GT_REGAD(SDRAM_PARA0)
	stwbrx	r6, 0, (r5)
        GT_REGAD(SDRAM_PARA1)
	stwbrx	r6, 0, (r5)
        GT_REGAD(SDRAM_PARA2)
	stwbrx	r6, 0, (r5)
        GT_REGAD(SDRAM_PARA3)
	stwbrx	r6, 0, (r5)

/*  Check if memory is registred or not and set up accordingly */

	lis	r5, HIADJ(MISC_MBSZ)
	lbz	r4, LO(MISC_MBSZ)(r5)
	andi.	r4, r4, 0x10
	beq	sdram_set_unbuffered

	DBGPRINTSTR("SDRAM Registred\r\n")
        GT_REGWR(SDRAM_CNFG, 0xecc38380)	/* Set registered */
	b	sdram_set_mode

sdram_set_unbuffered:
	DBGPRINTSTR("SDRAM Unbuffered\r\n")
        GT_REGWR(SDRAM_CNFG, 0xecc18380)	/* Set unbuffered */

sdram_set_mode:
        GT_REGWR(SDRAM_ADDRESS_DECODE, 2)	/* Address decode */
        GT_REGWR(SDRAM_OPERATION_MODE, 0)	/* Operation Mode normal */
/**/

/*
 *  Set up the cache snooping to do snooping on the entire SDRAM area.
 *  We use snoop 0 for internals, PCI0 and PCI1.
 */

#ifdef NO_SNOOP_FOR_SDMA_YET_BECAUSE_IT_IS_BROKEN

#define GT_SNOOP_WB     0x00020000
        GT_REGWR(SNOOP_BASE_ADDRESS_0, GT_SNOOP_WB | 0)
        GT_REGWR(SNOOP_TOP_ADDRESS_0, 0x0fff)
#endif

	/* 
	 *  PCI interface parameters
	 */

        GT_REGWR(PCI_0_TIME_OUT, 0x0000ffff)	/* TimeOut 0/1 (PCI_0) */

        GT_REGWR(PCI_1_TIME_OUT, 0x0000ffff)	/* TimeOut 0/1 (PCI_1) */

        GT_REGWR(PCI_0_BAR_EN, 0xfffff800)	/* pci0 BAR enable */

        GT_REGWR(PCI_1_BAR_EN, 0xfffff800)	/* pci1 BAR enable */


        sync

/* Well, what the.... */
	mfmsr	3
	INT_MASK(3, 4)		/* Disable interrupt */
	ori	r3, r3, 0x3002	/* set FP, ME and RI */
	mtmsr	3

/* Invalidate all TLB entries */
	addis	r3, 0, 0
	ori	r3, r3, 0		# set up counter at 0x00000000 
	addis	r5, 0, 0x8		# high bound of 0x00080000 for 750/7400
tlblp:	
	tlbie	3
	sync
	addi	r3, r3, 0x1000
	cmp	r0, 0, r3, 5		# check if all 128 TLBs invalidated yet
	blt	tlblp

/*
 *  We scrub memory to get rid of potential parity errors.  Only
 *  clear the first 1MB of memory which is where PMON lives.
 */
#ifdef NOTYET
	DBGPRINTSTR("clearing memory\r\n")

	lis	r15, 0x10		/* Clear first 1MB */
	srwi	r3, r15, 2		/* Mem size div 4 */
	li	r4, 0x4000		/* Start from 0x4000 to preserve */
	sub	r3, r3, 4		/* message areas */
	mtctr	3
1:
	stw	r4, 0(r4)		/* Zero out what will be the stack */
	addic	r4, r4, 0x4
	bdnz	1b
#endif


in_ram:

	bl	dbgled1_off
	DBGPRINTSTR("memory ok\r\n")

	lis	r4, HI(start)
	addi	r1, r4, -64		/* RAM START++ will be overwritten */
	stw	r15, 8(r1)		/* Save away memory size */
	add	r3, r4, r16
	bl	copytoram		/* Go do PPC initialization */
	cmpwi	r3, 0
	beq	__go

/* Turn on bitfail LED to show that mem init failed */
	b	bootinit_fail

/*
 *  All stations are GO for takeoff.
 *  Lets go to the other end of the universe!
 */
__go:
	DBGPRINTSTR("copy to ram ok\r\n")

	lwz	r3, 8(r1)			/* Memorysize */

	lis	r1, HIADJ(STACKBASE)
	addi	r1, r1, LO(STACKBASE)
	mtsprg	0, r1
	addi	r1, r1, STACKSIZE-64
	li	r0, 0x0		/* Mark end of frames on stack */
	stw	r0, 0(r1)
	stw	r0, 4(r1)

	lis	r4, HIADJ(initppc)
	addi	r4, r4, LO(initppc)
	mtlr	4
	blr

/**/
bootinit_nomem:
	PRINTSTR("PMON2000 PowerPC ABORT! No RAM memory found!\r\n")
1:
	bl	dbgled0_on	/* FLASH 111 <-> 001 - NO RAM */
	DELAY(10000000)
	bl	dbgled0_off
	DELAY(10000000)
	b	1b

bootinit_fail:
	PRINTSTR("PANIC! Verify after copy to ram failed!\r\n")
1:
	bl	dbgled0_on	/* FLASH 111 <-> 010 - RAM COPY ERR */
	DELAY(10000000)
	bl	dbgled0_off
	DELAY(10000000)
	b	1b

/*
 *  Simple serial output routine used to communicate messages
 *  during prom setup before 'real' driver is running.
 *  This code simply displays a string of chars on the console.
 */

	.globl	serial_out
serial_out:
	GT_REGWR(BRG0_CFG_REG, 0x002100d8)	/* 9600 baud 133Mhz Tclk */
	GT_REGWR(BRG0_BAUD_TUNING_REG, 0x0)

	GT_REGWR(MPSC0_MAIN_CONFIGURATION_LOW, 0x04c4)
	GT_REGWR(MPSC0_MAIN_CONFIGURATION_HIGH, 0x06400600)
	GT_REGWR(MPSC0_PROTOCOL_CONFIGURATION, 0x00003000)

	GT_REGWR(CHANNEL0_REGISTER4, 0x20000000)
	GT_REGWR(CHANNEL0_REGISTER5, 0x00009000)
	
	lis	r30, HIADJ(COM1_BASE_ADDR)
	addi	r30, r30, LO(COM1_BASE_ADDR)

	lis	r31, 0x0002	/* let things stabilize */
	mtctr	31
1:
	bdnz	1b

2:
	lbz	r31, 0(r3)
	cmpwi	r31, 0
	beq	5f

	lbz	r31, 0(r3)
	li	r29, 12
	stwbrx	r31, r29, r30	/* send char */
	IORDER
	li	r29, 16
	lwbrx	r31, r29, r30
	ori	r31, r31, 0x0200
	stwbrx	r31, r29, r30
4:
	lwbrx	r31, r29, r30
	andi.	r31, r31, 0x0200
	bne	4b

	addi	r3, r3, 1
	b	2b
5:
	blr			/* return */

	.globl	tgt_putchar
tgt_putchar:
	lis	r9, HIADJ(COM1_BASE_ADDR)
	addi	r9, r9, LO(COM1_BASE_ADDR)

	li	r10, 12
	stwbrx	r3, r10, r9	/* send char */
	IORDER
	li	r10, 16
	lwbrx	r0, r10, r9
	ori	r0, r0, 0x0200
	stwbrx	r0, r10, r9
1:
	lwbrx	r0, r10, r9
	andi.	r0, r0, 0x0200
	bne	1b

	blr

put_hex_word:
	or	r4, r3, 3
	mflr	5
	srwi	r3, r4, 28
	bl	put_hex
	srwi	r3, r4, 24
	bl	put_hex
	srwi	r3, r4, 20
	bl	put_hex
	srwi	r3, r4, 16
	bl	put_hex
	srwi	r3, r4, 12
	bl	put_hex
	srwi	r3, r4, 8
	bl	put_hex
	srwi	r3, r4, 4
	bl	put_hex
	or	r3, r4, 4
	bl	put_hex
	li	r3, 32
	bl	tgt_putchar
	mtlr	5
	blr

put_hex:
	andi.	r3, r3, 0xf
	lis	r9, HIADJ(hexchars)
	addi	r9, r9, LO(hexchars)
	add	r9, r9, r3
	add	r9, r9, r16
	lbz	r3, 0(r9)
	b	tgt_putchar

	.rodata
hexchars:
	.ascii	"0123456789abcdef"

	.text

dbgled0_off:
	lis	r5, HIADJ(MISC_FCR)
	lbz	r4, LO(MISC_FCR)(r5)
	andi.	r4, r4, 0xfe
	stb	r4, LO(MISC_FCR)(r5)
	blr

dbgled1_off:
	lis	r5, HIADJ(MISC_FCR)
	lbz	r4, LO(MISC_FCR)(r5)
	andi.	r4, r4, 0xfd
	stb	r4, LO(MISC_FCR)(r5)
	blr

dbgled0_on:
	lis	r5, HIADJ(MISC_FCR)
	lbz	r4, LO(MISC_FCR)(r5)
	ori	r4, r4, 0x01
	stb	r4, LO(MISC_FCR)(r5)
	blr

dbgled1_on:
	lis	r5, HIADJ(MISC_FCR)
	lbz	r4, LO(MISC_FCR)(r5)
	ori	r4, r4, 0x02
	stb	r4, LO(MISC_FCR)(r5)
	blr
	blr