start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: start.S,v 1.1 2002/11/07 15:24:20 pefo Exp $ */

/*
 * Copyright (c) 2000-2002 Opsycon AB  (www.opsycon.se)
 * Copyright (c) 2001 Allegro Networks, Inc.(www.allegronetworks.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#include "target/pmon_target.h"
#include <pmon/dev/gt64260reg.h>
#include <machine/mpc_regs.h>
#include <machine/psl.h>
#include <machine/cpu.h>

#ifndef INT_MASK
#define INT_MASK(src, des)	rlwinm	des, src, 0, r17, 15
#endif	/* INT_MASK */

#define	HID0	1008
#define	HID1	1009
#define	L2CR	1017
#define	CTR	9
#define	PVR	287

#define HIADJ(x)	(x)@ha
#define HI(x)		(x)@h
#define LO(x)		(x)@l

/*
 *   Register usage:
 *
 *   r0		scratch
 *   r1		stack pointer
 *   r2		scratch
 *   r3 - r4	BAT macros
 *   r5 - r6	GT64260 macros
 *
 *   r12-r13	scratch
 *   r14	processor type (from PVR reg)
 *   r15	memory size accumulator
 *   r16	load offset
 *   r25	GT64260 base address
 *   r30-r31	serial port scratch registers.
 */
/*
 *  Use this macro to prevent reordering by as/ld and processor
 */
#define	IORDER		eieio; sync

/*
 *  Macros used to setup BAT regs.
 */
#define IBAT_SETUP(batno, batuval, batlval)	\
	lis r3, HIADJ(batuval); addi r3, r3, LO(batuval);	\
	lis r4, HIADJ(batlval); addi r4, r4, LO(batlval);	\
	isync; mtibatu batno, 3; isync; mtibatl batno, 4; sync

#define DBAT_SETUP(batno, batuval, batlval)	\
	lis r3, HIADJ(batuval); addi r3, r3, LO(batuval);	\
	lis r4, HIADJ(batlval); addi r4, r4, LO(batlval);	\
	isync; mtdbatu batno, 3; isync; mtdbatl batno, 4; sync


/* Delay macro */
#define	DELAY(cnt)	\
	lis 0, HI(cnt);	\
	ori 0,0,LO(cnt);\
	mtctr 0;	\
1:			\
	bdnz	1b	\

/*
 *  Use to print a string. Only when UART is around.
 *  Note that this macro uses the link register so save
 *  it before using this macro if a blr depends on it...
 */
#if !defined(GT_UART)
#define PRINTSTR(str)		\
	bl	9f;		\
	.asciz	str;		\
	.align	2;		\
9:	 mflr	r3;		\
	bl	serial_out
#else
#define PRINTSTR(str)
#endif

#ifdef BOOT_TRACE
#define	DBGPRINTSTR(str)	PRINTSTR(str)
#else
#define	DBGPRINTSTR(str)
#endif

/*************************************************************
 *NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE*
 *************************************************************
 *  Throughout this code r25 is used to hold the GT-chip base
 *  address. DON'T use r25 for any purpose whatsoever!
 */

/*
 *  Macros to simplify setting up the Galileo controller
 */
#define GT_REGAD(offs) \
        ori     r5, r25, offs

#define GT_REGWR(offs, value)           \
        ori     r5, r25, offs;          \
        lis     r6, HIADJ(value);       \
        addi    r6, r6, LO(value);      \
        stwbrx  r6, 0, (r5);		\
	eieio; sync

/*
 *  Link start is 0x10000. Pad up to reset vector.
 */
	.space	0x100

	.globl	_start
	.globl	start
_start:
start:

	.globl	pmon_stack
stack = start - 0x4000		/* 16K PMON stack */
pmon_stack = start		/* Top of stack */
	.globl	pmon_intstack
intstack = stack - 0x2000	/* 8k PMON interrupt stack */
pmon_intstack = stack		/* Top of stack */


/* Clear MSR to diable interrupts and checks */

	andi.	r1, r1, 0x0
	sync
	mtmsr	1		/* Clear MSR, turns off any translation etc */
	isync

/* XXX Normally we get here after a hard reset an caches are off
 * XXX per hardware specification. However we want to give ourselfs
 * XXX a slight chance to softload and debug this code.
 */
	mfspr	r3, HID0
	lis	r4, 0xffff
	ori	r4, r4, 0x3fff
	and	r3, r3, r4
	sync
	isync
	mtspr	HID0, r3	/* Turn off L1 caches */
	sync
	isync

	mtspr	L2CR, r1	/* Turn off L2 cache */
	sync
	isync


/*
 *  Clear mapping registers to delete any unwanted mappings.
 */
	li	r1, 0x0
	mtibatu	0, r1
	mtibatl	0, r1
	mtibatu	1, r1
	mtibatl	1, r1
	mtibatu	2, r1
	mtibatl	2, r1
	mtibatu	3, r1
	mtibatl	3, r1
	mtdbatu	0, r1
	mtdbatl	0, r1
	mtdbatu	1, r1
	mtdbatl	1, r1
	mtdbatu	2, r1
	mtdbatl	2, r1
	mtdbatu	3, r1
	mtdbatl	3, r1
	isync
	sync

	lis	r1, 0x8000
	isync
	mtsr	sr0, r1
	mtsr	sr1, r1
	mtsr	sr2, r1
	mtsr	sr3, r1
	mtsr	sr4, r1
	mtsr	sr5, r1
	mtsr	sr6, r1
	mtsr	sr7, r1
	mtsr	sr8, r1
	mtsr	sr9, r1
	mtsr	sr10, r1
	mtsr	sr11, r1
	mtsr	sr12, r1
	mtsr	sr13, r1
	mtsr	sr14, r1
	mtsr	sr15, r1
	isync
	sync
	sync

/*
 *  Get processor type
 */
	mfspr	r14, PVR
	rlwinm	r14, r14, 16, 16, 31	/* Get 16 msb */

	cmpwi	r14, CPU_TYPE_750
	beq	init_750
	cmpwi	r14, CPU_TYPE_7400
	beq	init_750
	cmpwi   r14, CPU_TYPE_750FX
	beq     init_750FX

	b	init_unknown_cpu

init_750FX:
	li	r1, 0x0
	mtspr	560, r1		/*	mtibatu	4, r1 */
	mtspr	561, r1		/*	mtibatl	4, r1 */
	mtspr	562, r1		/*	mtibatu	5, r1 */
	mtspr	563, r1		/*	mtibatl	5, r1 */
	mtspr	564, r1		/*	mtibatu	6, r1 */
	mtspr	565, r1		/*	mtibatl	6, r1 */
	mtspr	566, r1		/*	mtibatu	7, r1 */
	mtspr	567, r1		/*	mtibatl	7, r1 */
	mtspr	568, r1		/*	mtdbatu	4, r1 */
	mtspr	569, r1		/*	mtdbatl	4, r1 */
	mtspr	570, r1		/*	mtdbatu	5, r1 */
	mtspr	571, r1		/*	mtdbatl	5, r1 */
	mtspr	572, r1		/*	mtdbatu	6, r1 */
	mtspr	573, r1		/*	mtdbatl	6, r1 */
	mtspr	574, r1		/*	mtdbatu	7, r1 */
	mtspr	575, r1		/*	mtdbatl	7, r1 */
	isync
	sync

	
init_750:
	mfspr	r3, HID0
	lis	r4, 0xffff
	ori	r4, r4, 0x3fff
	and	r3, r3, r4
	sync
	isync
	mtspr	HID0, r3		/* Turn off L1 caches */
	sync
	isync

	li	r4, 0x0c00
	or	r3, r3, r4
	mtspr	HID0, r3		/* Clear L1 caches */

/* Set r16 to the load vs link offset. */

init_unknown_cpu:
	bl	1f
1:
	mflr	r3
	lis	r16, 0xffff
	and.	r16, r16, r3
	lis	r4, HI(start)
	sub	r16, r16, r4		/* R16 is now load offset */

/*
 *  Find out if executing in ROM or RAM.
 */

	lis	r4, 0xf000		/* Last 256Mb segment */
	and.	r4, r4, r3
	lis	r15, 0x0200		/* 32MB default for ramloaded */
	beq	in_ram			/* We are ram loaded! */

/*
 *  We are executing from ROM. We have to create the WORLD as we want it!
 *  Start by doing GT chip selects and SDRAM initilization.
 *
 *  Set up the internal address for the GT64260. For a large memory
 *  system we would like to have it high up in memory to allow the
 *  lower memory space to hold a contigous area of our memory.
 *  We also set up r25 to point at the base address.
 */
        lis     r5, HI(GT_BASE_ADDR_DEFAULT)
        ori     r5, r5, INTERNAL_SPACE_DECODE
        lis     r6, 0x100                       # no swapping
        ori     r6, r6, (GT_BASE_ADDR >> 20)
        stwbrx  r6, 0, (r5)
        lis     r25, HI(GT_BASE_ADDR)
/**/
        GT_REGAD(CPU_CONF)		/*  CPU interface parameters, */
        lwbrx   r6, 0, (r5)		/*  change from default */

	oris	r6, r6, 0x4000		/* Sysclock synchronous */
	ori	r6, r6, 0xa000		/* AACK and TA delays */

        stwbrx  r6, 0, (r5)
        sync
/**/
	/* MPP interface parameters */
        GT_REGWR(MPP_CNTRL0, 0x53547777)
        GT_REGWR(MPP_CNTRL1, 0x44009911)
        GT_REGWR(MPP_CNTRL2, 0x40098888)
        GT_REGWR(MPP_CNTRL3, 0x00090066)
        GT_REGWR(GPP_LEVEL_CNTRL, 0x000002c6)
/**/
	GT_REGWR(MAIN_ROUTING_REGISTER, 0x00000038)
	GT_REGWR(RECEIVE_CLOCK_ROUTING_REGISTER, 0x0)
	GT_REGWR(TRANSMIT_CLOCK_ROUTING_REGISTER, 0x0)
        GT_REGWR(SER_PORTS_MUX, 0x00010101)	/* Serial Ports Mpx - MII */
        GT_REGWR(ETH_PHY_ADDR_REG, 0x00000020)	/* MII PHY Addresses */
/**/
        GT_REGWR(GT_DEV0_PAR, 0xcdcfdfff)
        GT_REGWR(GT_DEV1_PAR, 0xcdcfdfff)
        GT_REGWR(GT_DEV2_PAR, 0xcdcfdfff)
        GT_REGWR(GT_DEV3_PAR, 0xcdcfdfff)
        GT_REGWR(GT_BOOT_PAR, 0xcdcfdfff)

	GT_REGWR(CS_0_LOW_DECODE_ADDRESS, CS0_BASE >> 20)
	GT_REGWR(CS_0_HIGH_DECODE_ADDRESS, (CS0_BASE + CS0_SIZE - 1) >> 20)
	GT_REGWR(CS_1_LOW_DECODE_ADDRESS, CS1_BASE >> 20)
	GT_REGWR(CS_1_HIGH_DECODE_ADDRESS, (CS1_BASE + CS1_SIZE - 1) >> 20)
	GT_REGWR(CS_2_LOW_DECODE_ADDRESS, CS2_BASE >> 20)
	GT_REGWR(CS_2_HIGH_DECODE_ADDRESS, (CS2_BASE + CS2_SIZE - 1) >> 20)
/**/
	bl	dbgled0_on
	bl	dbgled1_on

/* Now we can start to print on serial console (if present) */
	PRINTSTR("\r\n\r\n\r\nPMON2000 PowerPC Initializing. Standby...\r\n")

	GT_REGWR(CS_3_LOW_DECODE_ADDRESS, FLASH_BASE >> 20)
	GT_REGWR(CS_3_HIGH_DECODE_ADDRESS, (FLASH_BASE + FLASH_SIZE - 1) >> 20)
	GT_REGWR(BOOTCS_LOW_DECODE_ADDRESS, BOOT_BASE >> 20)
	GT_REGWR(BOOTCS_HIGH_DECODE_ADDRESS, (BOOT_BASE + BOOT_SIZE - 1) >> 20)

cont_init:
	xor	r0, r0, r0

/*
 *  Configure SDRAM. 
 */

	DBGPRINTSTR("Probing SDRAM config\r\n")

	lis	r5, HIADJ(MISC_MBSZ)
	lbz	r4, LO(MISC_MBSZ)(r5)

	andi.	r0, r4, 0x07
        lis	r17, 0x400
        slw	r17, r17, r0  		/* Compute bank size */

	li	r18, 0			/* Assume single bank */
	andi.	r0, r4, 0xc0
	beq	1f
	or	r18, r17, r17
1:
	add	r15, r17, r18


/*
 *  Note! Dual bank code left in for possible future expansion.
 *  This code assumes that both memory modules (if two are used) are
 *  of the same type, size and speed.