puma.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: puma.h,v 1.3 2003/06/11 13:07:52 pefo Exp $ */

/*
 * Copyright (c) 2000-2002 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _EV64260_H_
#define _EV64260_H_

/*
 *  Define top of PMON-land. PMON will not use memory above this
 *  address but leave it alone for applications.
 */
//#define	PMON_TOP		0x00200000	/* 2MB */

/*
 *  CS space mapping.
 */
#ifdef GT_HIGH
#define	GT_BASE_ADDR		0x70000000
#define	CS0_BASE		0x70100000
#define	CS0_SIZE		0x00100000
#define	CS1_BASE		0x70200000
#define	CS1_SIZE		0x00100000
#define	CS2_BASE		0x1d000000
#define	CS2_SIZE		0x01000000
#define	FLASH_BASE		0x70400000
#define	FLASH_SIZE		0x00800000
#define	RTC_BASE		0x70200000
#define	RTC_SIZE		0x00800000
#else
#define	SRAM_BASE		0x1c000000
#define	SRAM_SIZE		0x00800000
#define	RTC_BASE		0x1c800000
#define	RTC_SIZE		0x00800000
#define	UART_BASE		0x1d000000
#define	UART_SIZE		0x00800000
#define	FLASH_BASE		0x1a000000
#define	FLASH_SIZE		0x02000000
#endif
#define	BOOT_BASE		0xfe000000
#define	BOOT_SIZE		0x02000000

/*
 *  PCI Bus allocation
 */
#define PCI0_MEM_SPACE_BASE     0xc0000000
#define PCI0_MEM_SPACE_SIZE     0x10000000
#define PCI0_IO_SPACE_BASE      0xe0000000
#define PCI0_IO_SPACE_SIZE      0x08000000

#define PCI1_MEM_SPACE_BASE     0xd0000000
#define PCI1_MEM_SPACE_SIZE     0x10000000
#define PCI1_IO_SPACE_BASE      0xe8000000
#define PCI1_IO_SPACE_SIZE      0x08000000

#define	ISA_IO_BASE		PCI_IO_BASE

/*
 *  NVRAM mapping
 */
#ifdef NVRAM_IN_FLASH

#define	NVRAM_SIZE		0x00010000
#define	NVRAM_SECSIZE		0x00010000
#define	NVRAM_OFFS		0x00000000
#define NVRAM_VXWORKS		(NVRAM_OFFS + NVRAM_SIZE)

#else	/* Use clock ram, 2048 bytes only */
#define	NVRAM_SECSIZE		2048
#define	NVRAM_OFFS		0x200
#define	ETHER_LOC		0x784		/* Ethernet address base */
#define	ETHER_OFFS		0x584
#define	NVRAM_SIZE		(ETHER_LOC - NVRAM_OFFS)
#define NVRAM_VXWORKS		0x100
#endif

#define NVRAM_VXWORKS_DEFAULT \
"wancom(0,0)host:/usr/vw/config/puma/vxWorks h=90.0.0.3 e=90.0.0.50 u=target"

#define	GT_DM_FLASH	FLASH_BASE

/*
 *  Device module discouart defs.
 */
#define GTSYSCLK        133000000       /* Sysclock HZ */

#define COM1_BASE_ADDR	(0x70008000)	/* Com 1 */
#define COM2_BASE_ADDR	(UART_BASE + 0x00)	/* Com 2 */
#define GT_COM1   	1 
#define GT_COM2   	2 

#define	MISC_AREV	(CS0_BASE + 0x0000)
#define	MISC_PREV	(CS0_BASE + 0x0001)
#define	MISC_MBSZ	(CS0_BASE + 0x0002)
#define	MISC_RST	(CS0_BASE + 0x0003)
#define	MISC_FCR	(CS0_BASE + 0x0004)
#  define MISC_FCR_LED0	0x01
#  define MISC_FCR_LED1	0x02
#  define MISC_FCR_BWEN	0x20
#  define MISC_FCR_BOEN	0x40
#define	MISC_MARCH	(CS0_BASE + 0x0005)
#define	MISC_GPR	(CS0_BASE + 0x0006)


#endif