start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

check_if_128:
	cmpwi	12, 0x20
	bne	check_if_256
/* Bank 128 */
	MPC_CFG_WR(MPC107_CFG_MSTA_03, 0x00008000)
	MPC_CFG_WR(MPC107_CFG_MSTA_47, 0x00008000)
	MPC_CFG_WR(MPC107_CFG_EMSTA_03, 0x01010000)
	MPC_CFG_WR(MPC107_CFG_EMSTA_47, 0x03030202)
	MPC_CFG_WR(MPC107_CFG_MEND_03, 0xff7fff7f)
	MPC_CFG_WR(MPC107_CFG_MEND_47, 0xff7fff7f)
	MPC_CFG_WR(MPC107_CFG_EMEND_03, 0x01010000)
	MPC_CFG_WR(MPC107_CFG_EMEND_47, 0x03030202)
	lis	15, 0x0800		/* Memory size accumulator  = 64MB */
	li	4, 1
	b	memdone

check_if_256:
	cmpwi	12, 0x40
	bne	fallback_to_64
/* Bank 256*/
	MPC_CFG_WR(MPC107_CFG_MSTA_03, 0x00000000)
	MPC_CFG_WR(MPC107_CFG_MSTA_47, 0x00000000)	/* XXX Check... */
	MPC_CFG_WR(MPC107_CFG_EMSTA_03, 0x03020100)
	MPC_CFG_WR(MPC107_CFG_EMSTA_47, 0x03030303)
	MPC_CFG_WR(MPC107_CFG_MEND_03, 0xffffffff)
	MPC_CFG_WR(MPC107_CFG_MEND_47, 0xffffffff)
	MPC_CFG_WR(MPC107_CFG_EMEND_03, 0x03020100)
	MPC_CFG_WR(MPC107_CFG_EMEND_47, 0x03030303)
	lis	15, 0x1000		/* Memory size accumulator  = 64MB */
	li	4, 1
/**/
memdone:
	MPC_CFG_AD(MPC107_CFG_MBEN)	/* Bank enables */
	stb	4, (MPC107_CFG_MBEN & 3)(21)
/**/
	MPC_CFG_AD(MPC107_CFG_MPMR)
	li	4, 0x8a			/* 100Mhz */
	stb	4, (MPC107_CFG_MPMR & 3)(21)
/**/
	MPC_CFG_AD(MPC107_CFG_ODCR)
	li	4, (PCI50OHM|CPU40OHM|MEM13OHM|PCICLK13OHM|MEMCLK13OHM)
	stb	4, (MPC107_CFG_ODCR & 3)(21)
/**/
	MPC_CFG_AD(MPC107_CFG_CDCR)
	li	4, 0x0203
	sthbrx	4, 0, 21
/**/
	MPC_CFG_AD(MPC107_CFG_MDCR)
	li	4, 0
	stb	4, (MPC107_CFG_MDCR & 3)(21)
/**/
	li	4, 10000
	mtctr	4
1:
	bdnz	1b		/* Delay to allow memory to initialize */
/**/
	MPC_CFG_RD(MPC107_CFG_MCFG1)
	oris	4, 4, 0x0008
	MPC_CFG_RWR(MPC107_CFG_MCFG1)
/**/
	li	4, 10000
	mtctr	4
1:
	bdnz	1b		/* Delay to allow memory to initialize */

/* Output any message */
	add	4, 18, 16
	bl	serial_out

	lis	4, HIADJ(main_msg)	/* Output 'alive' message on console */
	addi	4, 4, LO(main_msg)
	add	4, 4, 16
	bl	serial_out

/*
 *  We scrub memory used by PMON2000 to get rid of potential parity errors.
 */
	li	4, 0x4000		/* Start from 0x4000 to preserve */
	sub	3, 3, 4			/* message areas */
	lis	3, HI((CLIENTPC - 0x4000) / 4)
	ori	3, 3, LO((CLIENTPC - 0x4000) / 4)
	mtctr	3
1:
	stw	4, 0(4)
	addic	4, 4, 0x4
	bdnz	1b
	b	do_copy

/*
 *  RAM memory should now be operational, we can call C-code (some
 *  restrictions still do apply, like usage of initialised vars).
 */
in_ram:
	lis	4, HIADJ(ram_msg)
	addi	4, 4, LO(ram_msg)
	add	4, 4, 16
	bl	serial_out

do_copy:
	lis	4, HI(start)
	addi	1, 4, -64		/* RAM START++ will be overwritten */
	stw	15, 8(1)		/* Save away memory size */

	add	3, 4, 16
	bl	copytoram		/* Go do PPC initialization */

	cmpwi	3, 0x0
	beq	__go			/* Verify after copy succeded */

	or	18, 3, 3
	bl	put_hex_word
	lwz	3, 0(18)
	bl	put_hex_word
	sub	18, 18, 16
	lwz	3, 0(18)
	bl	put_hex_word

	lis	4, HIADJ(fail_msg)
	addi	4, 4, LO(fail_msg)
	b	bootinit_fail
/*
 *  All stations are GO for takeoff.
 *  Lets go to the other end of the universe!
 */
__go:
	lis	3, HIADJ(CM4_SOP)
	lbz	4, LO(CM4_SOP)(3)
	ori	4, 4, CM4_SOP_BIT
	stb	4, LO(CM4_SOP)(3)

	lwz	3, 8(1)			/* Memorysize */

	mfspr	4, HID0	
	ori	4, 4, 0x00a4
	isync			/* Serialize disable and branch history enab */
	mtspr	HID0, 4	
	isync

	lis	1, HIADJ(STACKBASE)
	addi	1, 1, LO(STACKBASE)
	mtsprg	0, 1
	addi	1, 1, STACKSIZE-64
	li	0, 0x0		/* Mark end of frames on stack */
	stw	0, 0(1)
	stw	0, 4(1)

	lis	4, HIADJ(initppc)
	addi	4, 4, LO(initppc)
	mtlr	4
	blr


	.rodata
main_msg:
	.asciz	"\r\nPMON2000 PowerPC Initializing. Standby...\r\n"
ram_msg:
	.asciz	"\r\nPMON2000 PowerPC Ram Loaded. Standby...\r\n"
fail_msg:
	.asciz	"Copy to ram failed to verify, halting!\r\n"
noboot_msg:
	.ascii	"\r\n!!! User boot area disabled       !!!\r\n"
	.asciz	"!!! Emergency boot loader called  !!!\r\n"
badcrc_msg:
	.ascii	"\r\n!!! CRC error in bootrom detected !!!\r\n"
	.asciz	"!!! Emergency boot loader called  !!!\r\n"
empty_msg:
	.asciz	"\r\n"

	.section ".text"
	.align	2
/**/
bootinit_fail:
	add	4, 4, 16
	bl	serial_out

	lis	3, HIADJ(CM4_SOP)
	lbz	4, LO(CM4_SOP)(3)
	ori	4, 4, CM4_SOP_BIT
	xori	4, 4, CM4_SOP_BIT
	stb	4, LO(CM4_SOP)(3)

#ifdef MPC_DEBUG
	lis	20, HI(MPC107_CONF_ADDR)
	ori	21, 20, LO(MPC107_CONF_DATA)
	ori	20, 20, LO(MPC107_CONF_ADDR)
	lis	22, 0x8000		/* config space access enable */

	lis	4, HIADJ(x70)
	addi	4, 4, LO(x70)
	add	4, 4, 16
	bl	serial_out
	MPC_CFG_RD3(0x70)
	bl	put_hex_word
	MPC_CFG_RD3(0x74)
	bl	put_hex_word
	MPC_CFG_RD3(0x78)
	bl	put_hex_word
	MPC_CFG_RD3(0x7c)
	bl	put_hex_word
	
	lis	4, HIADJ(x80)
	addi	4, 4, LO(x80)
	add	4, 4, 16
	bl	serial_out
	MPC_CFG_RD3(0x80)
	bl	put_hex_word
	MPC_CFG_RD3(0x84)
	bl	put_hex_word
	MPC_CFG_RD3(0x88)
	bl	put_hex_word
	MPC_CFG_RD3(0x8c)
	bl	put_hex_word
	
	lis	4, HIADJ(x90)
	addi	4, 4, LO(x90)
	add	4, 4, 16
	bl	serial_out
	MPC_CFG_RD3(0x90)
	bl	put_hex_word
	MPC_CFG_RD3(0x94)
	bl	put_hex_word
	MPC_CFG_RD3(0x98)
	bl	put_hex_word
	MPC_CFG_RD3(0x9c)
	bl	put_hex_word
	
	lis	4, HIADJ(xf0)
	addi	4, 4, LO(xf0)
	add	4, 4, 16
	bl	serial_out
	MPC_CFG_RD3(0xf0)
	bl	put_hex_word
	MPC_CFG_RD3(0xf4)
	bl	put_hex_word
	MPC_CFG_RD3(0xf8)
	bl	put_hex_word
	MPC_CFG_RD3(0xfc)
	bl	put_hex_word
	
	lis	4, HIADJ(xa0)
	addi	4, 4, LO(xa0)
	add	4, 4, 16
	bl	serial_out
	MPC_CFG_RD3(0xa0)
	bl	put_hex_word
	MPC_CFG_RD3(0xa4)
	bl	put_hex_word
	MPC_CFG_RD3(0xa8)
	bl	put_hex_word
	MPC_CFG_RD3(0xac)
	bl	put_hex_word
	
	.rodata
cr_lf:	.asciz	"\r\n"
x70:	.asciz	"\r\n70-7f -> "
x80:	.asciz	"\r\n80-8f -> "
x90:	.asciz	"\r\n90-9f -> "
xf0:	.asciz	"\r\nf0-ff -> "
xa0:	.asciz	"\r\na0-af -> "
	.section ".text"
	.align	2
#endif
1:
	b	1b

/**/

/*
 *  Simple serial output routine used to communicate messages
 *  during prom setup before 'real' driver is running.
 *  This code simply displays a string of chars on the console.
 */

serial_out:
	lis	30, HIADJ(COM1_BASE_ADDR)
	addi	30, 30, LO(COM1_BASE_ADDR)
	li	31, 1
	stb	31, 4(30)	/* DTR on */
	IORDER
	li	31, 0x80	/* Get to divisor latch */
	stb	31, 3(30)
	IORDER
	li	31, NS16550HZ/(16*CONS_BAUD)
	stb	31, 0(30)
	IORDER
	li	31, 0x0
	stb	31, 1(30)
	IORDER
	li	31, 0x3		/* 8 bits no parity */
	stb	31, 3(30)
	IORDER

	lis	31, 0x0002	/* let sio stabilize */
	mtctr	31
1:
	bdnz	1b

2:
	lbz	31, 0(4)
	cmpwi	31, 0x0
	beq	4f
3:
	lbz	31, 5(30)
	andi.	31, 31, 0x20
	beq	3b		/* Wait for tx buffer empty */

	lbz	31, 0(4)
	stb	31, 0(30)	/* send char */
	IORDER
	addi	4, 4, 1
	b	2b

4:
	blr			/* return */
/**/

put_hex_word:
	or	4, 3, 3
	mflr	5
	srwi	3, 4, 28
	bl	put_hex
	srwi	3, 4, 24
	bl	put_hex
	srwi	3, 4, 20
	bl	put_hex
	srwi	3, 4, 16
	bl	put_hex
	srwi	3, 4, 12
	bl	put_hex
	srwi	3, 4, 8
	bl	put_hex
	srwi	3, 4, 4
	bl	put_hex
	or	3, 4, 4
	bl	put_hex
	li	3, 32
	bl	tgt_putchar
	mtlr	5
	blr
	
put_hex:
	andi.	3, 3, 0xf
	lis	9, HIADJ(hexchars)
	addi	9, 9, LO(hexchars)
	add	9, 9, 3
	add	9, 9, 16
	lbz	3, 0(9)
	b	tgt_putchar

	.rodata
hexchars:
	.ascii	"0123456789abcdef"

	.section ".text"
	.align	2

	.globl	tgt_putchar
tgt_putchar:
	lis	9, HIADJ(COM1_BASE_ADDR)
	addi	9, 9, LO(COM1_BASE_ADDR)
1:
	lbz	0, 5(9)
	andi.	0, 0, 0x20
	beq	1b

	stb	3, 0(9)
	blr

/**/
	.globl	ppc_enableL2cache
ppc_enableL2cache:
	sync
	mfspr	3, L2CR
	sync
	lis	4, 0xffff
	ori	4, 4, 0xfe00
	and.	3, 3, 4
	oris	3, 3, 0x8000
	sync
	mtspr	L2CR, 3
	sync

	blr
/**/
/**/

/*
 *  I2C code for reading out the contents of the SPD eeprom.
 *  Very rudimentary and not intended to be general purpose!
 *  Reads one byte at specified offset.
 */

	.globl	i2c_init
i2c_init:
	lis	9, HIADJ(MPC107_I2C_ADR)
	addi	10, 9, LO(MPC107_I2C_CCR)
	lwbrx	3, 0, 10
	andi.	3, 3, ~I2C_CCR_MEN & 0xffff	/* Disable */
	stwbrx	3, 0, 10

	addi	10, 9, LO(MPC107_I2C_FDR)
	lwbrx	3, 0, 10
	lis	0, 0xffff
	ori	0, 0, 0xffc0
	and	3, 3, 0
	ori	3, 3, 0x31		/* Frequency divider */
	stwbrx	3, 0, 10

	addi	10, 9, LO(MPC107_I2C_ADR)
	lwbrx	3, 0, 10
	lis	0, 0xffff
	ori	0, 0, 0xffc0
	and	3, 3, 0
	ori	3, 3, 0x02		/* Set slave address */
	stwbrx	3, 0, 10

	addi	10, 9, LO(MPC107_I2C_CCR)
	lwbrx	3, 0, 10
	ori	3, 3, 0x80		/* Master enable */
	stwbrx	3, 0, 10
	blr
/**/

/* 3 = offs */
	.globl	i2c_read
i2c_read:
	lis	9, HIADJ(MPC107_I2C_ADR)
	addi	10, 9, LO(MPC107_I2C_CSR)
	li	0, 0x0
	stwbrx	0, 0, 10		/* Clear status */
	IORDER

	addi	10, 9, LO(MPC107_I2C_CCR)
	li	0, I2C_CCR_MEN|I2C_CCR_MSTA|I2C_CCR_MTX
	stwbrx	0, 0, 10		/* Startup! */
	IORDER

	addi	10, 9, LO(MPC107_I2C_CDR)
	li	0, 0xa0			/* Write access + slave addr 0x50 */
	stwbrx	0, 0, 10
	IORDER

1:
	addi	10, 9, LO(MPC107_I2C_CSR)
	lwbrx	0, 0, 10		/* Read status */
	andi.	0, 0, I2C_CSR_MIF	/* Check interrupt MSTA */
	beq	1b			/* 0 == Nothing yet */

	li	0, 0x0
	stwbrx	0, 0, 10		/* Clear status */
	IORDER

	addi	10, 9, LO(MPC107_I2C_CDR)
	stwbrx	3, 0, 10		/* Output offset */
	IORDER

2:
	addi	10, 9, LO(MPC107_I2C_CSR)
	lwbrx	0, 0, 10		/* Read status */
	andi.	2, 0, I2C_CSR_MIF	/* Check interrupt MSTA */
	beq	2b			/* 0 == Nothing yet */

	li	0, 0x0
	stwbrx	0, 0, 10		/* Clear status */
	IORDER

	addi	10, 9, LO(MPC107_I2C_CCR)
	lwbrx	0, 0, 10
	ori	0, 0, I2C_CCR_RSTA
	stwbrx	0, 0, 10		/* Restart */
	IORDER

	addi	10, 9, LO(MPC107_I2C_CDR)
	li	0, 0xa1			/* Read access + slave addr 0x50 */
	stwbrx	0, 0, 10
	IORDER

3:
	addi	10, 9, LO(MPC107_I2C_CSR)
	lwbrx	0, 0, 10		/* Read status */
	andi.	0, 0, I2C_CSR_MIF	/* Check interrupt MSTA */
	beq	3b			/* 0 == Nothing yet */

	li	0, 0x0
	stwbrx	0, 0, 10		/* Clear status */
	IORDER

	addi	10, 9, LO(MPC107_I2C_CCR)
	lwbrx	0, 0, 10
	andi.	0, 0, ~(I2C_CCR_MTX|I2C_CCR_RSTA) & 0xffff
	ori	0, 0, I2C_CCR_TXAK
	stwbrx	0, 0, 10
	IORDER

	addi	10, 9, LO(MPC107_I2C_CDR)
	lwbrx	0, 0, 10
	IORDER

4:
	addi	10, 9, LO(MPC107_I2C_CSR)
	lwbrx	0, 0, 10		/* Read status */
	andi.	0, 0, I2C_CSR_MIF	/* Check interrupt MSTA */
	beq	4b			/* 0 == Nothing yet */

	addi	10, 9, LO(MPC107_I2C_CCR)
	lwbrx	0, 0, 10
	andi.	0, 0, ~I2C_CCR_MSTA & 0xffff
	stwbrx	0, 0, 10
	IORDER

	addi	10, 9, LO(MPC107_I2C_CDR)
	lwbrx	3, 0, 10

	lis	0, 1
	mtctr	0
1:
	bdnz	1b			/* Delay to settle */

	blr