start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	lis	0, 0x000f
	ori	0, 0, 0xffff
	and	4, 4, 0		
	oris	4, 4, 0x0730
	MPC_CFG_RWR(MPC107_CFG_MCFG3)

	/* Set up Memory Control Configuration Register 4 */
	MPC_CFG_RD(MPC107_CFG_MCFG4)
	andi.	0, 0, 0
	lis	0, 0x0083
	and	4, 4, 0
	oris	4, 4, 0x2536
	ori	4, 4, 0x2220
	MPC_CFG_RWR(MPC107_CFG_MCFG4)
#endif
	/* Set up Output Driver Control Register */
	MPC_CFG_AD(MPC107_CFG_ODCR)
	li	4, (MEM13OHM | PCICLK8OHM | MEMCLK8OHM)
	stb	4, (MPC107_CFG_ODCR & 3)(21)
	sync
	
	/* Set up CLK Driver Control Register */
	MPC_CFG_AD(MPC107_CFG_CDCR)
	li	4, 0x7d09
	ori	4, 4, 0x8000
	sthbrx	4, 0, 21

	/* Set up Miscellaeous I/O Control Register */
	MPC_CFG_AD(MPC107_CFG_MDCR)
	li	4, 0
	stb	4, (MPC107_CFG_MDCR & 3)(21)

	/* Delay */
	li	4, 10000
	mtctr	4
1:
	bdnz	1b		/* Delay to allow memory to initialize */

	/* Enable RAM interface logic */
	MPC_CFG_RD(MPC107_CFG_MCFG1)
	oris	4, 4, 0x0008
	MPC_CFG_RWR(MPC107_CFG_MCFG1)

	/* Delay */
	li	4, 10000
	mtctr	4
1:
	bdnz	1b		/* Delay to allow memory to initialize */
	
/*
 *  Here we need to enable the IBAT/DBAT (after setup) to be able to
 *  access 0xfff00000+ if processor is 740/750/7400!
 */
        IBAT_SETUP(0, 0x00001fff, 0x0000001a)	/* Ram segment */
        IBAT_SETUP(1, 0xf0001fff, 0xf000002a)	/* Boot rom segment */
        IBAT_SETUP(2, 0x00000000, 0x00000000)	/* Disable */
        IBAT_SETUP(3, 0x00000000, 0x00000000)	/* Disable */
        DBAT_SETUP(0, 0x00001fff, 0x0000001a)	/* Ram segment */
        DBAT_SETUP(1, 0x80001fff, 0x8000002a)	/* PCI mem */
        DBAT_SETUP(2, 0x70001fff, 0x7000002a)	/* Extended ROM/Flash */
        DBAT_SETUP(3, 0xf0001fff, 0xf000002a)	/* PCI I/O, Boot rom segment */

	mfmsr	4
	ori	4, 4, 0x0010	/* Translation enable */
	isync
	mtmsr	4
	sync

	/* Check the total size of Dram and reconfigure controller */
/*	bl	sizeDram*/
#if 1
	/* Enable L1 data cache */
	mfspr	4, HID0	
	ori	4, 4, LO(HID0_ICE | HID0_DCE | HID0_SGE | HID0_BTIC | HID0_BHTE)	/* Enable D-cache */
	isync
	mtspr	HID0, 4	
	isync
/*
 *  Set up on chip L2 cache controller.
 */
	lis	4, HI(L2CR_L2SIZ_1024 | L2CR_L2CLK_3 | L2CR_L2RAM_PIPE)
	ori	4, 4, 0x0000
	
	mtspr	L2CR, 4
	sync
	mfspr	5, L2CR
	oris	5, 5, HI(L2CR_L2I)
	mtspr	L2CR, 5
	sync
	
2:
	mfspr	3, L2CR
	andi.	3, 3, LO(L2CR_L2IP)
	cmpwi	3, LO(L2CR_L2IP)
	beq	2b		/* Wait for invalidate done */
#if 0
/**/
	li	0, 0x780		/* PLL lockup wait */
	mtctr	0
3:
	bdnz	3b
#endif
/**/
	oris	4, 4, HI(L2CR_L2E)
	mtspr	L2CR, 4			/* Enable L2 cache */
	sync
	isync
#endif

/* Output 'alive' message on console */
	lis	4, HIADJ(main_msg)
	addi	4, 4, LO(main_msg)
	add	4, 4, 16
	bl	serial_out

/*
 *  We scrub the entire memory to get rid of potential parity errors.
 */
#if 0	
	lis	15, 0x10		/* Clear first 1MB */
	srwi	3, 15, 2		/* Mem size div 4 */
	li	4, 0x4000		/* Start from 0x4000 to preserve */
	sub	3, 3, 4		/* message areas */
	mtctr	3
1:
	stw	4, 0(4)		/* Zero out what will be the stack */
	addic	4, 4, 0x4
	bdnz	1b
#endif
	b	in_rom
/*
 *  RAM memory should now be operational, we can call C-code (some
 *  restrictions still do apply, like usage of initialised vars).
 */
	.globl in_ram
in_ram:
	lis	4, HIADJ(ram_msg)
	addi	4, 4, LO(ram_msg)
	add	4, 4, 16
	bl	serial_out

#if 0	
	/* Check the total size of Dram and reconfigure controller */
	bl	sizeDram
#endif
	.globl in_rom
in_rom:	
	lis	4, HI(start)
	addi	1, 4, -64		/* RAM START++ will be overwritten */
	stw	15, 8(1)		/* Save away memory size */

	add	3, 4, 16
	bl	copytoram		/* Go do PPC initialization */

	cmpwi	3, 0x0
	beq	__go			/* Verify after copy succeded */

	or	18, 3, 3
	bl	put_hex_word
	lwz	3, 0(18)
	bl	put_hex_word
	sub	18, 18, 16
	lwz	3, 0(18)
	bl	put_hex_word

	lis	4, HIADJ(fail_msg)
	addi	4, 4, LO(fail_msg)
	b	bootinit_fail
/*
 *  All stations are GO for takeoff.
 *  Lets go to the other end of the universe!
 */
__go:
	lwz	3, 8(1)			/* Memorysize */

	lis	1, HIADJ(STACKBASE)
	addi	1, 1, LO(STACKBASE)
	mtsprg	0, 1
	addi	1, 1, LO(STACKSIZE-64)
	li	0, 0x0		/* Mark end of frames on stack */
	stw	0, 0(1)
	stw	0, 4(1)

	lis	4, HIADJ(initppc)
	addi	4, 4, LO(initppc)
	mtlr	4
	blr


	.rodata
main_msg:
	.asciz	"\r\n\r\nPMON2000 PowerPC Initializing. Standby...\r\n"
ram_msg:
	.asciz	"\r\n\r\nPMON2000 PowerPC Ramloaded. Standby...\r\n"
fail_msg:
	.asciz	" <= PANIC! Verify after copy to ram failed!\r\n"

	.section ".text"
	.align	2
/**/
bootinit_fail:
	add	4, 4, 16
	bl	serial_out
1:
	b	1b

	.section ".text"
	.align	2
	
/**/

/*
 *  Simple serial output routine used to communicate messages
 *  during prom setup before 'real' driver is running.
 *  This code simply displays a string of chars on the console.
 */

serial_out:
	lis	30, HIADJ(COM1_BASE_ADDR)
	addi	30, 30, LO(COM1_BASE_ADDR)
	li	31, 1
	stb	31, 4(30)	/* DTR on */
	IORDER
	li	31, 0x80	/* Get to divisor latch */
	stb	31, 3(30)
	IORDER
#ifdef POCONO
	li	31, 0x78	/* Baud rate */
#else
	li	31, 0x50	/* Baud rate */
#endif
	stb	31, 0(30)
	IORDER
	li	31, 0x0
	stb	31, 1(30)
	IORDER
	li	31, 0x3		/* 8 bits no parity */
	stb	31, 3(30)
	IORDER

	lis	31, 0x0002	/* let sio stabilize */
	mtctr	31
1:
	bdnz	1b

2:
	lbz	31, 0(4)
	cmpwi	31, 0x0
	beq	4f
3:
	lbz	31, 5(30)
	andi.	31, 31, 0x20
	beq	3b		/* Wait for tx buffer empty */

	lbz	31, 0(4)
	stb	31, 0(30)	/* send char */
	IORDER
	addi	4, 4, 1
	b	2b

4:
	blr			/* return */
/**/

	.globl	put_hex_word
put_hex_word:
	or	4, 3, 3
	mflr	5
	srwi	3, 4, 28
	bl	put_hex
	srwi	3, 4, 24
	bl	put_hex
	srwi	3, 4, 20
	bl	put_hex
	srwi	3, 4, 16
	bl	put_hex
	srwi	3, 4, 12
	bl	put_hex
	srwi	3, 4, 8
	bl	put_hex
	srwi	3, 4, 4
	bl	put_hex
	or	3, 4, 4
	bl	put_hex
	li	3, 32
	bl	tgt_putchar
	mtlr	5
	blr
	
put_hex:
	andi.	3, 3, 0xf
	lis	9, HIADJ(hexchars)
	addi	9, 9, LO(hexchars)
	add	9, 9, 3
	add	9, 9, 16
	lbz	3, 0(9)
	b	tgt_putchar

	.rodata
hexchars:
	.ascii	"0123456789abcdef"

	.section ".text"
	.align	2

	.globl	tgt_putchar
tgt_putchar:
	lis	9, HIADJ(COM1_BASE_ADDR)
	addi	9, 9, LO(COM1_BASE_ADDR)
1:
	lbz	0, 5(9)
	andi.	0, 0, 0x20
	beq	1b

	stb	3, 0(9)
	blr

/*
 * -------------------------    Size DRAM ------------------------------------------  
 *
 * Above code already setup DRAM as 256MB
 *
 * Write patterns at:
 * 	256MB -4, 128MB -4, 64MB, -4
 *  If patterns read/verify then have 256MB
 *   else set 128MB (bank zero end address ).
 */

#define SIZE256MB	0x10000000
#define SIZE128MB	0x08000000
#define SIZE64MB	0x04000000
sizeDram:
	# Set up Addresses  

 	lis	2, HI(SIZE256MB)
	ori	2, 2, LO(SIZE256MB)
	addi	2, 2, -4

 	lis	3, HI(SIZE128MB)
	ori	3, 3, LO(SIZE128MB)
	addi	3, 3,-4

 	lis	4, HI(SIZE64MB)
	ori	4, 4, LO(SIZE64MB)
	addi	4, 4, -4

	# Set up Patterns  

	or	5, 2, 2
	or	6, 3, 3
	or	7, 4, 4

	oris	5, 5, 0x0256
	oris	6, 6, 0x0128
	oris	7, 7, 0x0064

	# Write Patterns  

	stw     5, 0(2)
	stw     6, 0(3)
	stw     7, 0(4)
	sync

	lwz	1, 0(2)
	cmplw   5, 1
	bne     set128			# bif 256MB Pattern fail  

	lwz	1, 0(3)
	cmplw   6, 1
	bne     set128			# bif 128MB Pattern fail  

	lwz	1, 0(4)
	cmplw   7, 1
	bne     set128			# bif 64MB Pattern fail  

	/* Here if all patterns verify, there is 256MB */

	b	dramContinue

set128:
	/* Fixed regs 20 = PCI CONFIG ADDR, 21 = PCI_CONFIG_DATA, 22 = CONF DEV */
	lis	20, HI(MPC107_CONF_ADDR)
	lis	21, HI(MPC107_CONF_DATA)
	lis	22, 0x8000		/* config space access enable */

	/* Set End Addr of Banks 0 to 128MB */
	MPC_CFG_WR(MPC107_CFG_MEND_03,  0xff7f3f7f)
	lis	15, 0x0800		/* Memory size accumulator = 128 MB */
	
dramContinue:
        blr