power4e.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$OpenBSD$ */

/*
 * Copyright (c) 2000 Opsycon AB  (www.opsycon.se)
 * Copyright (c) 2000 Rtmx, Inc   (www.rtmx.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for Rtmx, Inc by
 *	Opsycon Open System Consulting AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _POWER4E_H_
#define _POWER4E_H_

/*
 *  This is the offset from where PMON is linked to the boot rom area
 */
#define	RAM_START	0x00010000
#define	ROM_START	0xfff00000
#define	LINK_OFFSET	(ROM_START - RAM_START)


/*
 *  PCI Bus allocation
 */
#define	PCI_MEM_BASE		0xc0000000
#define	PCI_MEM_SIZE		(0xff000000-PCI_MEM_BASE)
#define	PCI_IO_BASE		0x80000000
#define	PCI_IO_SIZE		(0x80800000-PCI_IO_BASE)

/*
 *  Timekeep device (M48T18) (also NVRAM)
 */
#define	NVRAM_SIZE		0x1ff8	/* How many bytes, clock cells excl. */
#define	NVRAM_BASE		(PCI_MEM_BASE + 0x000f0000)
#define	NVRAM_FIRST_ENV		(NVRAM_BASE + 0x0000)
#define	NVRAM_LAST_ENV		(NVRAM_BASE + 0x17ff)
#define	NVRAM_SIZE_ENV		(NVRAM_LAST_ENV - NVRAM_FIRST_ENV + 1)
#define NVRAM_VXWORKS		(NVRAM_BASE + NVRAM_SIZE - 512)
#define NVRAM_VXWORKS_DEFAULT \
"dc(0,0)host:/usr/vw/config/power4e/vxWorks h=90.0.0.3 e=90.0.0.50 u=target"
#define	NVRAM_ENETADDR		(NVRAM_BASE + 0x1cf2)

#define	M48T18_BASE		(NVRAM_BASE + 0x1ff8)
#define	HWSERIALNO		(NVRAM_BASE + 0x1ff2)

/*
 *  Super I/O ports.
 */
#define COM1_BASE_ADDR	(P4E_ISA_IO_BASE + 0x02e8)	/* Com 1 */
#define COM2_BASE_ADDR	(P4E_ISA_IO_BASE + 0x03e8)	/* Com 2 */
#define NS16550HZ	(1843200 / 3)

/*
 * Some MPC106 defines
 */
#define	MPC106_BASE	0x80000000
#define	MPC106_CFG_ADDR	(MPC106_BASE + 0xcf8)
#define MPC106_CFG_DATA	(MPC106_BASE + 0xcfc)

#define	MPC106_REG_PCI_CMD	0x04	/* PCI command register */
#define	MPC106_REG_PCI_STAT	0x06	/* PCI status register */
#define	MPC106_REG_REV		0x08	/* Device revision register */
#define	MPC106_REG_MCFG1	0xf0	/* Memory config1 register */
#define	MPC106_REG_MCFG2	0xf4	/* Memory config2 register */
#define	MPC106_REG_MCFG3	0xf8	/* Memory config3 register */
#define	MPC106_REG_MCFG4	0xfc	/* Memory config4 register */
#define	MPC106_REG_MBEN		0xa0	/* Memory bank enable register */
#define	MPC106_REG_MSTA_03	0x80
#define	MPC106_REG_MSTA_47	0x84
#define	MPC106_REG_EMSTA_03	0x88
#define	MPC106_REG_EMSTA_47	0x8c
#define	MPC106_REG_MEND_03	0x90
#define	MPC106_REG_MEND_47	0x94
#define	MPC106_REG_EMEND_03	0x98
#define	MPC106_REG_EMEND_47	0x9c
#define	MPC106_REG_CFG_A8	0xa8
#define	MPC106_REG_CFG_AC	0xac

/* MPC106 A-mapping */
#define P4E_ISA_IO_BASE	0x80000000	/* Start of ISA I/O space */

/* Power.4e ports */
#define	P4E_MISC	(P4E_ISA_IO_BASE + 0x01f4)
#define	P4E_MISC_MEM	0xe0
#define	P4E_MISC_MEM_32EDO	0x00
#define	P4E_MISC_MEM_16EDO	0x20
#define	P4E_MISC_MEM_32FPM	0x40
#define	P4E_MISC_MEM_16FPM	0x60
#define	P4E_MISC_MEM_128EDO	0x80
#define	P4E_MISC_MEM_64EDO	0xa0
#define	P4E_MISC_FWP		0x04


/* CPU configuration status register */
#define	P4E_CFG		(P4E_ISA_IO_BASE + 0x0800)
#define	P4E_CFG_L2	0x03	/* Level 2 cache size */
#define	P4E_CFG_L2_IS_512K	0x00
#define	P4E_CFG_L2_IS_256K	0x01
#define	P4E_CFG_L2_IS_1M	0x02
#define	P4E_CFG_L2_NONE		0x03
#define	P4E_CFG_BUS	0x0c	/* Bus frequency */
#define	P4E_CFG_BUS_IS_33	0x00
#define	P4E_CFG_BUS_IS_40	0x04
#define	P4E_CFG_BUS_IS_50	0x08
#define	P4E_CFG_BUS_IS_60	0x0c
#define	P4E_CFG_CPU	0xf0	/* Cpu version */
#define	P4E_CFG_CPU_IS_601	0x00
#define	P4E_CFG_CPU_IS_602	0x10
#define	P4E_CFG_CPU_IS_603	0x20
#define	P4E_CFG_CPU_IS_604	0x30

/* Mezzaine configuration status */
#define	P4E_MEZZ_CFG	(P4E_ISA_IO_BASE + 0x01f6)
#define	P4E_MEZZ1	0x07
#define	P4E_MEZZ1_32EDO		0x00
#define	P4E_MEZZ1_16EDO		0x01
#define	P4E_MEZZ1_32FPM		0x02
#define	P4E_MEZZ1_16FPM		0x03
#define	P4E_MEZZ1_128EDO	0x04
#define	P4E_MEZZ1_64EDO		0x05	
#define	P4E_MEZZ2	0x38
#define	P4E_MEZZ2_32EDO		(0x00 << 3)
#define	P4E_MEZZ2_16EDO		(0x01 << 3)
#define	P4E_MEZZ2_32FPM		(0x02 << 3)
#define	P4E_MEZZ2_16FPM		(0x03 << 3)
#define	P4E_MEZZ2_128EDO	(0x04 << 3)
#define	P4E_MEZZ2_64EDO		(0x05 << 3)
#endif