pci_machdep.c

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: pci_machdep.c,v 1.1 2002/09/03 11:22:54 pefo Exp $ */

/*
 * Copyright (c) 2000 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */
#include <sys/param.h>
#include <sys/device.h>
#include <sys/systm.h>

#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>

#include <machine/pio.h>

#include <pmon/dev/mpc106reg.h>

#include <pmon.h>

/* PCI regions in PCI space */
#define PCI_IO_SPACE_PCI_BASE	0x00000000
#define PCI_MEM_SPACE_PCI_BASE	0x00000000
#define	_256MB (256*1024*1024)

/* PCI mem regions in PCI space */
#define PCI_LOCAL_MEM_PCI_BASE	0x80000000	/* CPU Mem accessed from PCI */

/* soft versions of above */
static pcireg_t pci_local_mem_pci_base;

static pcireg_t _pci_conf_readn(pcitag_t, int, int);
static void _pci_conf_writen(pcitag_t, int, pcireg_t, int);
extern int _pciverbose;
extern void *pmalloc(size_t);

extern char hwethadr[6];

static struct pci_bus *_pci_bus[16];
static int  _max_pci_bus = 0;

struct pci_intline_routing iroute = {
	0, 0, 0,
	{
	 { 0, 0, 0, 0}, { 9, 0, 0, 0}, { 6, 0, 0, 0}, {14, 0, 0, 0},
	 {15, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0},
	 { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0},
	 { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0},
	 { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0},
	 { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0},
	 { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0},
	 { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0}, { 0, 0, 0, 0},
	},
	NULL
};

/*
 * Called to initialise the bridge at the beginning of time
 */
int
_pci_hwinit(initialise, iot, memt)
	int initialise;
	bus_space_tag_t iot;
	bus_space_tag_t memt;
{
	struct pci_device *pd;
	struct pci_bus *pb;

	iot->bus_base = PA_TO_VA(PCI_IO_BASE);
	iot->bus_reverse = 1;
	memt->bus_base = PA_TO_VA(PCI_MEM_BASE);
	memt->bus_reverse = 1;

	pci_local_mem_pci_base = PCI_LOCAL_MEM_PCI_BASE;

	if (!initialise) {
		return(0);
	}

	/*
	 * Initialize PCI Head device (Northbridge).
	 */
	pd = pmalloc(sizeof(struct pci_device));
	if(pd == NULL) {
		printf("pci: can't alloc memory for northbridge\n");
		return(-1);
	}

	pd->pa.pa_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
	pd->pa.pa_iot = iot;
	pd->pa.pa_memt = memt;
	pd->pa.pa_dmat = &bus_dmamap_tag;
	_pci_head = pd;

	pd->bridge.secbus = pmalloc(sizeof(struct pci_bus));
	if(pd->bridge.secbus == NULL) {
		printf("pci: can't alloc memory for new pci bus\n");
		return(-1);
	}

	pb = pd->bridge.secbus;
	pb->max_lat = 255;
	pb->fast_b2b = 1;
	pb->prefetch = 1;
	pb->bandwidth = 4000000;
	pb->ndev = 1;
	_pci_bushead = pb;
	_pci_bus[0] = pb;
	_max_pci_bus = 1;

	/* point to start and end of region (leaving bottom 16M for ISA) */
	pb->minpcimemaddr  = PCI_MEM_SPACE_PCI_BASE + 0x1000000;
	pb->nextpcimemaddr = PCI_MEM_SPACE_PCI_BASE + _256MB;

	/*
	 * leave 512M at beginning of PCI i/o space for ISA bridge (it
	 * actually uses only 64K, but this is needed for a ISA DMA 
	 * h/w fix which needs a higher address bit to spot ISA cycles).
	 */
	pb->minpciioaddr  = PCI_IO_SPACE_PCI_BASE + 0x80000;
	pb->nextpciioaddr = PCI_IO_SPACE_PCI_BASE + _256MB;

	/* Interrupt routing */
	_pci_inthead = &iroute;

	return(1);
}


/*
 * Called to reinitialise the bridge after we've scanned each PCI device
 * and know what is possible. We also set up the interrupt controller
 * routing and level control registers.
 */
void
_pci_hwreinit (void)
{
	int level;

	/* SBS really twisted the interrupt lines. Be careful! */
	_pci_conf_write(_pci_make_tag(0, 0, 0), 0x60, 0x0e06090f);
	level = (1L << 15) | (1L << 14) | (1L << 6) | (1L << 9);
	outb(PCI_IO_BASE + 0x04d0, level);
	outb(PCI_IO_BASE + 0x04d1, level >> 8);
}

void
_pci_flush (void)
{
}


/*
 *  Map the CPU virtual address of an area of local memory to a PCI
 *  address that can be used by a PCI bus master to access it.
 */
vm_offset_t
_pci_dmamap(va, len)
	vm_offset_t va;
	unsigned int len;
{
	return(pci_local_mem_pci_base + VA_TO_PA (va));
}

/*
 *  Map the PCI address of an area of local memory to a CPU physical
 *  address.
 */
vm_offset_t
_pci_cpumap(pcia, len)
	vm_offset_t pcia;
	unsigned int len;
{
	return(pcia - pci_local_mem_pci_base);
}

/*
 *  Make pci tag from bus, device and function data.
 */
pcitag_t
_pci_make_tag(bus, device, function)
	int bus;
	int device;
	int function;
{
	pcitag_t tag;

	tag = (bus << 16) | (device << 11) | (function << 8);
	return(tag);
}

/*
 *  Break up a pci tag to bus, device function components.
 */
void
_pci_break_tag(tag, busp, devicep, functionp)
	pcitag_t tag;
	int *busp;
	int *devicep;
	int *functionp;
{
	if (busp) {
		*busp = (tag >> 16) & 255;
	}
	if (devicep) {
		*devicep = (tag >> 11) & 31;
	}
	if (functionp) {
		*functionp = (tag >> 8) & 7;
	}
}

int
_pci_canscan (pcitag_t tag)
{
    return (1);
}

/*
 *  Read a value form PCI configuration space. Support for
 *  all three data sizes (byte, halfword and word) is provided.
 */
static pcireg_t
_pci_conf_readn(tag, reg, width)
	pcitag_t tag;
	int reg;
	int width;
{
	pcireg_t data;
	u_int32_t addr;
	void *addrp;
	int bus, device, function;

	if (reg & (width-1) || reg < 0 || reg >= 0x100) {
		if (_pciverbose >= 1) {
			_pci_tagprintf (tag, "_pci_conf_read: bad reg 0x%x\r\n", reg);
		}
		return ~0;
	}

	_pci_break_tag (tag, &bus, &device, &function); 
	if (bus == 0) {
		/* Type 0 configuration on onboard PCI bus */
		if (device > 11 || function > 7) {
			return ~0;		/* device out of range */
		}
		addr = (1 << (device+11)) | (function << 8) | reg;
	}
	else {
		return ~0;		/* bus out of range */
	}

	addrp = (void *)(MPC106_PCI_CONF_SPACE + addr);

	switch (width) {
	case 1:
		data = (pcireg_t)in8rb(addrp);
		break;

	case 2:
		data = (pcireg_t)in16rb(addrp);
		break;

	default:
	case 4:
		data = (pcireg_t)in32rb(addrp);
		break;
	}
/* XXX We should prolly check error status here but what the... */


    return data;
}


pcireg_t
_pci_conf_read(pcitag_t tag, int reg)
{
    return _pci_conf_readn (tag, reg, 4);
}

/*
 *  Write a value to PCI configuration space. Support for
 *  all three data sizes (byte, halfword and word) is provided.
 */
static void
_pci_conf_writen(tag, reg, data, width)
	pcitag_t tag;
	int reg;
	pcireg_t data;
	int width;
{
    u_int32_t addr;
    void *addrp;
    int bus, device, function;

	if (reg & (width-1) || reg < 0 || reg >= 0x100) {
		if (_pciverbose >= 1) { 
			_pci_tagprintf(tag, "_pci_conf_write: bad reg %x\r\n", reg);
		}
		return;
	}

	_pci_break_tag (tag, &bus, &device, &function);

	if (bus == 0) {
		/* Type 0 configuration on onboard PCI bus */
		if (device > 5 || function > 7) {
			return;		/* device out of range */
		}
		addr = (1 << (device+11)) | (function << 8) | reg;
	}
	else {
		return;			/* bus out of range */
	}

	addrp = (void *)(MPC106_PCI_CONF_SPACE + addr);

	switch (width) {
	case 1:
		out8rb(addrp,  data);
		break;

	case 2:
		out16rb(addrp, data);
		break;

	default:
	case 4:
		out32rb(addrp, data);
		break;
	}
/* XXX We should prolly check error status here but what the... */

}

void
_pci_conf_write(pcitag_t tag, int reg, pcireg_t data)
{
    _pci_conf_writen (tag, reg, data, 4);
}

void *
_pci_map_int(tag, level, func, arg)
	pcitag_t tag;
	int level;
	int (*func) __P((void *));
	void *arg;
{
	pcireg_t data;
	int pin, bus, device;

	data = _pci_conf_read(tag, PCI_INTERRUPT_REG);

	pin = PCI_INTERRUPT_PIN(data);

	if (pin == 0) {
		/* No IRQ used. */
		return NULL;
	}

	if (pin > 4) {
		if (_pciverbose >= 1) {
			_pci_tagprintf (tag, "_pci_map_int: bad interrupt pin %d\r\n", pin);
		}
		return(NULL);
	}


	_pci_break_tag (tag, &bus, &device, NULL);

	if (bus != 0 || device > 5) {
		return(NULL);
	}

	/* XXX need to work this out based on device number etc. */
	_pci_tagprintf(tag, "_pci_map_int: attempt to map device %d pin %c\n", 
		   device, '@' + pin);
	return(NULL);
}

/*-------------------------------------------------------------------------*/
/*
 * Code from "pci/if_de.c" used to calculate crc32 of ether rom data.
 */
#define      CRC32POLY  0xEDB88320UL
static __inline__ unsigned
srom_crc32(const unsigned char *databuf, size_t datalen)
{
	u_int idx, bit, data, crc = 0xFFFFFFFFUL;

	for (idx = 0; idx < datalen; idx++)
		for (data = *databuf++, bit = 0; bit < 8; bit++, data >>= 1)
			crc = (crc >> 1) ^ (((crc ^ data) & 1) ? CRC32POLY : 0);
	return crc;
}

/*
 *  Simple version of DEC ethernet SROM emulation routine.
 */
int
pci_ether_hw_addr(sc, p, b, s)
	void *sc;
        u_int8_t *p, b, s;
{
	int i;

	for(i = 0; i < 128; i++)
		p[i] = 0x00;
	p[18] = 0x03;   /* Srom version. */
	p[19] = 0x01;   /* One chip. */
	/* Next six, ethernet address. */
	bcopy(hwethadr, &p[20], 6);

	p[26] = 0x00;   /* Chip 0 device number */
	p[27] = 30;             /* Descriptor offset */
	p[28] = 00;
	p[29] = 00;             /* MBZ */
					/* Descriptor */
	p[30] = 0x00;   /* Autosense. */
	p[31] = 0x08;
	p[32] = 0xff;   /* GP cntrl */
	p[33] = 0x01;   /* Block cnt */
#define GPR_LEN 0
#define RES_LEN 0
	p[34] = 0x80 + 12 + GPR_LEN + RES_LEN;
	p[35] = 0x01;   /* MII PHY type */
	p[36] = 0x00;   /* PHY number 0 */
	p[37] = 0x00;   /* GPR Length */
	p[38] = 0x00;   /* Reset Length */
	p[39] = 0x00;   /* Media capabilities */
	p[40] = 0x78;   /* Media capabilities */
	p[41] = 0x00;   /* Autoneg advertisment */
	p[42] = 0x78;   /* Autoneg advertisment */
	p[43] = 0x00;   /* Full duplex map */
	p[44] = 0x50;   /* Full duplex map */
	p[45] = 0x00;   /* Treshold map */
	p[46] = 0x18;   /* Treshold map */

	i = (srom_crc32(p, 126) & 0xFFFF) ^ 0xFFFF;
	p[126] = i;
	p[127] = i >> 8;
	return(1);
}