start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	li	r7, 0x0032
	andi.	r0, r11, 0x2
	bne	settiming
	lis	r8, 0x2400

settiming:
	GT_REGAD(SDRAM_MODE)
	stwbrx	r7, 0, (r5)

	GT_REGWR(SDRAM_OPERATION, 0x3)
1:
	lwbrx	r6, 0, (r5)
	andi.	r6, r6, 0x7
	bne	1b				/* Wait for idle */

	lis	r6, 0x1811
	ori	r6, r6, 0x0780
	cmpwi	r9, 1
	bne	1f
	lis	r6, 0x0011
1:
	or	r6, r6, r8
	GT_REGAD(D_UNIT_CONTROL_LOW)
	lwbrx	r8, 0, (r5)
	andi.	r8, r8, 0x007f
	or	r6, r6, r8
	stwbrx	r6, 0, (r5)
	eieio;sync

	GT_REGWR(SDRAM_OPERATION, 0x3)
1:
	lwbrx	r6, 0, (r5)
	andi.	r6, r6, 0x7
	bne	1b				/* Wait for idle */

	srwi	r12, r17, 20		/* r12 = module size in MB */
	cmpwi	r17, 0
	bne	1f
	srwi	r12, r18, 20
1:
	lis	r6, 0
	ori	r6, r6, 0x0002
	cmpwi	r12, 64	
	beq	sdram_set_density
	cmpwi	r12, 128
	beq	sdram_set_density

	lis	r6, 0
	ori	r6, r6, 0x0012
	cmpwi	r12, 256
	beq	sdram_set_density
	cmpwi	r12, 512
	beq	sdram_set_density

	lis	r6, 0
	ori	r6, r6, 0x0022

sdram_set_density:
        GT_REGAD(SDRAM_ADDR_CONTROL)
	stwbrx	r6, 0, (r5)
	eieio;sync

	GT_REGWR(SDRAM_TIMING_CONTROL_LOW, 0x11511220);

/* Set up SDRAM address decoder and sizes */
	GT_REGAD(BASE_ADDR_ENABLE)	/* Turn off all SDRAM decoders */
        lwbrx   r6, 0, r5
	ori	r6, r6, 0x000e
	stwbrx	r6, 0, r5

/*  Configure MAIN SDRAM module if poulated */

	cmpwi	r17, 0
	beq	sdram_slot1_config

	DBGPRINTSTR("INIT MAIN SDRAM module\r\n")

	li	r3, 0x605		/* Get number of module banks */
	bl	boot_i2c_read
	cmpwi	r3, 2
	beq	sdram_slot0_2bank

	DBGPRINTSTR("Single bank\r\n")
	GT_REGWR(CS_0_BASE_ADDR, 0)	/* Module starts at address 0 */
	GT_REGAD(CS_0_SIZE)
	srwi	r6, r17, 16		/* Make end value for GT reg */
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	b	sdram_slot1_config

sdram_slot0_2bank:
	DBGPRINTSTR("Dual bank\r\n")
	GT_REGWR(CS_0_BASE_ADDR, 0)	/* Module starts at address 0 */
	GT_REGAD(CS_1_BASE_ADDR)
	srwi	r6, r17, 17		/* Half size to bank 2 */
	stwbrx	r6, 0, (r5) 
	GT_REGAD(CS_0_SIZE)
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	GT_REGAD(CS_1_SIZE)
	stwbrx	r6, 0, (r5) 

	GT_REGAD(BASE_ADDR_ENABLE)	/* Turn on bank 1 decoders */
        lwbrx   r6, 0, r5
	xori	r6, r6, 0x0002
	stwbrx	r6, 0, r5

/*  Configure SECONDARY SDRAM module if poulated */

sdram_slot1_config:

	cmpwi	r18, 0
	beq	sdram_set_param		/* empty */

	DBGPRINTSTR("INIT SECONDARY SDRAM module\r\n")

	li	r3, 0x405		/* Get number of module banks */
	bl	boot_i2c_read
	cmpwi	r3, 2
	beq	sdram_slot1_2bank

	DBGPRINTSTR("Single bank\r\n")
	GT_REGAD(CS_2_BASE_ADDR)	/* Module starts at address 0 */
	srwi	r6, r17, 16		/* Make end value for GT reg */
	stwbrx	r6, 0, (r5) 
	GT_REGAD(CS_2_SIZE)
	add	r6, r17, r18
	srwi	r6, r6, 16		/* Make end value for GT reg */
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 

	GT_REGAD(BASE_ADDR_ENABLE)	/* Turn on bank 1 decoders */
        lwbrx   r6, 0, r5
	xori	r6, r6, 0x0004
	stwbrx	r6, 0, r5

	b	sdram_set_param

sdram_slot1_2bank:
	DBGPRINTSTR("Dual bank\r\n")
	GT_REGAD(CS_2_BASE_ADDR)	/* Module starts at address 0 */
	srwi	r6, r17, 16		/* Make end value for GT reg */
	stwbrx	r6, 0, (r5) 
	GT_REGAD(CS_3_BASE_ADDR)
	srwi	r6, r17, 20
	srwi	r4, r18, 21
	add	r6, r6, r4
	stwbrx	r6, 0, (r5) 
	GT_REGAD(CS_2_SIZE)
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	GT_REGAD(CS_3_SIZE)
	add	r6, r17, r18
	srwi	r6, r6, 20		/* Make end value for GT reg */
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 

	GT_REGAD(BASE_ADDR_ENABLE)	/* Turn on bank 1 decoders */
        lwbrx   r6, 0, r5
	xori	r6, r6, 0x000c
	stwbrx	r6, 0, r5

sdram_set_param:

#if 0
/* Reduce driving strength for DDR data pads */
	GT_REGAD(SDRAM_DATA_PADS_CALIBRATION)
	lwbrx	r6, 0, (r5)
	oris	r6, r6, 0x8000
	stwbrx	r6, 0, (r5)
	eieio;sync
	lis	r3, 0xffff
	ori	r3, r3, 0x7c00
	and.	r6, r6, r3
	ori	r6, r6, 0x00a5
	stwbrx	r6, 0, (r5)
	eieio;sync
#endif
/**/
	li	r3, 4
	bl	dbglednum

#if 0
	/* 
	 *  PCI interface parameters
	 */

        GT_REGWR(PCI_0_TIME_OUT, 0x0000ffff)	/* TimeOut 0/1 (PCI_0) */

        GT_REGWR(PCI_1_TIME_OUT, 0x0000ffff)	/* TimeOut 0/1 (PCI_1) */

        GT_REGWR(PCI_0_BAR_EN, 0xfffff800)	/* pci0 BAR enable */

        GT_REGWR(PCI_1_BAR_EN, 0xfffff800)	/* pci1 BAR enable */
#endif

/* Set up MPP pins, Internal PCI arbiter configuration */
	GT_REGWR(MPP_CONTROL0, 0x02222222)
	GT_REGWR(MPP_CONTROL1, 0x11333011)	/* 0x00333000 external */
	GT_REGWR(MPP_CONTROL2, 0x40431111)	/* 0x40430000 external */
	GT_REGWR(MPP_CONTROL3, 0x00000044)

/**/
	mfmsr	3
	ori	r3, r3, 0x3002	/* set FP, ME and RI */
	mtmsr	3

/* Invalidate all TLB entries */
	addis	r3, 0, 0
	ori	r3, r3, 0		# set up counter at 0x00000000 
	addis	r5, 0, 0x8		# high bound of 0x00080000 for 750/7400
tlblp:	
	tlbie	3
	sync
	addi	r3, r3, 0x1000
	cmp	r0, 0, r3, 5		# check if all 128 TLBs invalidated yet
	blt	tlblp

/*
 *  We scrub memory to get rid of potential parity errors.  Only
 *  clear the first 1MB of memory which is where PMON lives.
 */
	DBGPRINTSTR("clearing memory\r\n")

	lis	r3, 0x10		/* Clear first 1MB */
	li	r4, 0x4000		/* Start from 0x4000 to preserve */
	sub	r3, r3, 4		/* message areas at */
	srwi	r3, r3, 2		/* Mem size div 4 */
	mtctr	3
	li	r5, 0
1:
	stw	r5, 0(r4)		/* Zero out what will be the stack */
	addic	r4, r4, 0x4
	bdnz	1b


in_ram:
	DBGPRINTSTR("memory ok\r\n")

	li	r3, 5
	bl	dbglednum

	lis	r4, HI(start)
	addi	r1, r4, -64		/* RAM START++ will be overwritten */
	stw	r15, 8(r1)		/* Save away memory size */
	add	r3, r4, r16
	bl	copytoram		/* Go do PPC initialization */
	cmpwi	r3, 0
	beq	__go

/* Turn on bitfail LED to show that mem init failed */
	b	bootinit_fail

/*
 *  All stations are GO for takeoff.
 *  Lets go to the other end of the universe!
 */
__go:
	DBGPRINTSTR("copy to ram ok\r\n")

	li	r3, 0
	bl	dbglednum

	lwz	r3, 8(r1)			/* Memorysize */

	lis	r1, HIADJ(STACKBASE)
	addi	r1, r1, LO(STACKBASE)
	mtsprg	0, r1				/* Save CPU info area pointer */
	addi	r1, r1, STACKSIZE-64
	li	r0, 0x0		/* Mark end of frames on stack */
	stw	r0, 0(r1)
	stw	r0, 4(r1)

	lis	r4, HIADJ(initppc)
	addi	r4, r4, LO(initppc)
	mtlr	4
	blr

#if defined(SMP)
/*
 *  We are cpu 1 in a SMP system!
 */
not_cpu_0:
	/* Invalidate all TLB entries */
	addis	r3, 0, 0
	ori	r3, r3, 0		# set up counter at 0x00000000 
	addis	r5, 0, 0x8		# high bound of 0x00080000 for 750/7400
1:	
	tlbie	3
	sync
	addi	r3, r3, 0x1000
	cmp	r0, 0, r3, 5		# check if all 128 TLBs invalidated yet
	blt	1b

	/* Get a stack */
	lis	r1, HIADJ(STACKBASE+STACKSIZE)
	addi	r1, r1, LO(STACKBASE+STACKSIZE)
	mtsprg	0, r1				/* Save CPU info area pointer */
	addi	r1, r1, STACKSIZE-64
	li	r0, 0x0		/* Mark end of frames on stack */
	stw	r0, 0(r1)
	stw	r0, 4(r1)

	lis	r4, HIADJ(initppcsmp)
	addi	r4, r4, LO(initppcsmp)
	mtlr	4
	blr
#endif


/**/
bootinit_nomem:
	PRINTSTR("PMON2000 PowerPC ABORT! No RAM memory found!\r\n")
1:
	li	r3, 7
	bl	dbglednum	/* FLASH 111 <-> 001 - NO RAM */
	DELAY(2000000)
	li	r3, 1
	bl	dbglednum
	DELAY(2000000)
	b	1b

bootinit_fail:
	PRINTSTR("PANIC! Verify after copy to ram failed!\r\n")
1:
	li	r3, 7
	bl	dbglednum	/* FLASH 111 <-> 010 - RAM COPY ERR */
	DELAY(10000000)
	li	r3, 2
	DELAY(10000000)
	b	1b

/*
 *  Simple serial output routine used to communicate messages
 *  during prom setup before 'real' driver is running.
 *  This code simply displays a string of chars on the console.
 */

	.globl	serial_out
serial_out:
	lis	r30, HIADJ(COM1_BASE_ADDR)
	addi	r30, r30, LO(COM1_BASE_ADDR)
	li	r31, 1
	#stb	r31, 4(r30)	/* DTR on */
	stb	r31, 16(r30)	/* DTR on */
	IORDER
	li	r31, 0x80	/* Get to divisor latch */
	#stb	r31, 3(r30)
	stb	r31, 12(r30)
	IORDER
	li	r31, NS16550HZ/(16*CONS_BAUD)
	stb	r31, 0(r30)
	IORDER
	li	r31, 0x0
	#stb	r31, 1(r30)
	stb	r31, 4(r30)
	IORDER
	li	r31, 0x3		/* 8 bits no parity */
	#stb	r31, 3(r30)
	stb	r31, 12(r30)
	IORDER

	lis	r31, 0x0002	/* let sio stabilize */
	mtctr	31
1:
	bdnz	1b

2:
	lbz	r31, 0(r3)
	cmpwi	r31, 0
	beq	4f
3:
	#lbz	r31, 5(r30)
	lbz	r31, 20(r30)
	andi.	r31, r31, 0x20
	beq	3b		/* Wait for tx buffer empty */

	lbz	r31, 0(r3)
	stb	r31, 0(r30)	/* send char */
	IORDER
	addi	r3, r3, 1
	b	2b
4:
	blr			/* return */

	.globl	tgt_putchar
tgt_putchar:
	lis	r9, HIADJ(COM1_BASE_ADDR)
	addi	r9, r9, LO(COM1_BASE_ADDR)
1:
	#lbz	r0, 5(r9)
	lbz	r0, 20(r9)
	andi.	r0, 0, 0x20
	beq	1b
	stb	r3, 0(r9)
	IORDER
	blr

put_hex_word:
	or	r4, r3, 3
	mflr	5
	srwi	r3, r4, 28
	bl	put_hex
	srwi	r3, r4, 24
	bl	put_hex
	srwi	r3, r4, 20
	bl	put_hex
	srwi	r3, r4, 16
	bl	put_hex
	srwi	r3, r4, 12
	bl	put_hex
	srwi	r3, r4, 8
	bl	put_hex
	srwi	r3, r4, 4
	bl	put_hex
	or	r3, r4, 4
	bl	put_hex
	li	r3, 32
	bl	tgt_putchar
	mtlr	5
	blr

put_hex:
	andi.	r3, r3, 0xf
	lis	r9, HIADJ(hexchars)
	addi	r9, r9, LO(hexchars)
	add	r9, r9, r3
	add	r9, r9, r16
	lbz	r3, 0(r9)
	b	tgt_putchar

	.rodata
hexchars:
	.ascii	"0123456789abcdef"

	.text

	.globl	dbglednum
dbglednum:
	andi.	r4, r3, 1
	bne	1f
	lis	r5, HIADJ(DBGLED0_OFF)
	stb	r5, LO(DBGLED0_OFF)(r5)
	b	2f
1:
	lis	r5, HIADJ(DBGLED0_ON)
	stb	r5, LO(DBGLED0_ON)(r5)
2:
	andi.	r4, r3, 2
	bne	1f
	lis	r5, HIADJ(DBGLED1_OFF)
	stb	r5, LO(DBGLED1_OFF)(r5)
	b	2f
1:
	lis	r5, HIADJ(DBGLED1_ON)
	stb	r5, LO(DBGLED1_ON)(r5)
2:
	andi.	r4, r3, 4
	bne	1f
	lis	r5, HIADJ(DBGLED2_OFF)
	stb	r5, LO(DBGLED2_OFF)(r5)
	b	2f
1:
	lis	r5, HIADJ(DBGLED2_ON)
	stb	r5, LO(DBGLED2_ON)(r5)
2:
	blr

/*
 *  Probe an SDRAM module for it's size. Returns size in Mbyte.
 *  Size is 'number of banks' * 'bank density' * 'number of module banks'
 */
probe_sdram_size:
	mflr	r10
	andi.	r11, r3, 0x700		/* module address */
	bl	boot_i2c_read
	cmpwi	r3, -1
	beq	sdram_probe_err		/* no module found */

	ori	r3, r11, 5
	bl	boot_i2c_read		/* get number of module banks */
	or	r12, r3, r3

	ori	r3, r11, 31
	bl	boot_i2c_read		/* get bank density */
	mullw	r12, r12, r3

	ori	r3, r11, 17
	bl	boot_i2c_read		/* get number of banks */
	mullw	r12, r12, r3

	lis	r3, HI(0x100000)
	mullw	r3, r3, r12

	mtlr	r10
	blr

sdram_probe_err:
	li	r3, 0
	mtlr	r10
	blr