start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: start.S,v 1.3 2002/11/07 15:05:23 pefo Exp $ */

/*
 * Copyright (c) 2000-2002 Opsycon AB  (www.opsycon.se)
 * Copyright (c) 2000-2001 Rtmx, Inc   (www.rtmx.com)
 * Copyright (c) 2001 Allegro Networks, Inc.(www.allegronetworks.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for Rtmx, Inc by
 *	Opsycon Open System Consulting AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#include "target/pmon_target.h"

#include <pmon/dev/ns16550.h>
#include <machine/mpc_regs.h>
#include <machine/psl.h>
#include <machine/cpu.h>

#define	HID0	1008
#define	HID1	1009
#define	L2CR	1017
#define	CTR	9
#define	PVR	287

#define HIADJ(x)	(x)@ha
#define HI(x)		(x)@h
#define LO(x)		(x)@l

/*
 *   Register usage:
 *
 *   r0		scratch
 *   r1		stack pointer
 *   r2		scratch
 *   r3 - r4	BAT macros
 *   r5 - r6	GT64260 macros
 *
 *   r12-r13	scratch
 *   r14	processor type (from PVR reg)
 *   r15	memory size accumulator
 *   r16	load offset
 *   r25	GT64260 base address
 *   r30-r31	serial port scratch registers.
 */
/*
 *  Use this macro to prevent reordering by as/ld and processor
 */
#define	IORDER		eieio; sync

/*
 *  Macros used to setup BAT regs.
 */
#define IBAT_SETUP(batno, batuval, batlval)	\
	lis r3, HIADJ(batuval); addi r3, r3, LO(batuval);	\
	lis r4, HIADJ(batlval); addi r4, r4, LO(batlval);	\
	isync; mtibatu batno, 3; isync; mtibatl batno, 4; sync

#define DBAT_SETUP(batno, batuval, batlval)	\
	lis r3, HIADJ(batuval); addi r3, r3, LO(batuval);	\
	lis r4, HIADJ(batlval); addi r4, r4, LO(batlval);	\
	isync; mtdbatu batno, 3; isync; mtdbatl batno, 4; sync


/* Delay macro */
#define	DELAY(cnt)	\
	lis 0, HI(cnt);	\
	ori 0,0,LO(cnt);\
	mtctr 0;	\
1:			\
	bdnz	1b	\

/*
 *  Use to print a string. Only when UART is around.
 *  Note that this macro uses the link register so save
 *  it before using this macro if a blr depends on it...
 */
#if !defined(GT_UART)
#define PRINTSTR(str)		\
	bl	9f;		\
	.asciz	str;		\
	.align	2;		\
9:	 mflr	r3;		\
	bl	serial_out
#else
#define PRINTSTR(str)
#endif

#define BOOT_TRACE
#ifdef BOOT_TRACE
#define	DBGPRINTSTR(str)	PRINTSTR(str)
#else
#define	DBGPRINTSTR(str)
#endif

/*************************************************************
 *NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE*
 *************************************************************
 *  Throughout this code r25 is used to hold the GT-chip base
 *  address. DON'T use r25 for any purpose whatsoever!
 */

/*
 *  Macros to simplify setting up the Galileo controller
 */
#define GT_REGAD(offs) \
        ori     r5, r25, offs

#define GT_REGWR(offs, value)           \
        ori     r5, r25, offs;          \
        lis     r6, HIADJ(value);       \
        addi    r6, r6, LO(value);      \
        stwbrx  r6, 0, (r5);		\
	eieio; sync

/*
 *  Link start is 0x10000. Pad up to reset vector.
 */
	.space	0x100

	.globl	_start
	.globl	start
_start:
start:
	isync

/* Clear MSR to diable interrupts and checks */

	andi.	r1, r1, 0x0
	sync
	mtmsr	r1		/* Clear MSR, turns off any translation etc */
	isync

/*
 *  Clear mapping registers to delete any unwanted mappings.
 */
	li	r1, 0x0
	mtibatu	0, r1
	mtibatl	0, r1
	mtibatu	1, r1
	mtibatl	1, r1
	mtibatu	2, r1
	mtibatl	2, r1
	mtibatu	3, r1
	mtibatl	3, r1
	mtdbatu	0, r1
	mtdbatl	0, r1
	mtdbatu	1, r1
	mtdbatl	1, r1
	mtdbatu	2, r1
	mtdbatl	2, r1
	mtdbatu	3, r1
	mtdbatl	3, r1
	isync
	sync

	lis	r1, 0x8000
	isync
	mtsr	sr0, r1
	mtsr	sr1, r1
	mtsr	sr2, r1
	mtsr	sr3, r1
	mtsr	sr4, r1
	mtsr	sr5, r1
	mtsr	sr6, r1
	mtsr	sr7, r1
	mtsr	sr8, r1
	mtsr	sr9, r1
	mtsr	sr10, r1
	mtsr	sr11, r1
	mtsr	sr12, r1
	mtsr	sr13, r1
	mtsr	sr14, r1
	mtsr	sr15, r1
	isync
	sync
	sync

/*
 *  Get processor type
 */
	mfspr	r14, PVR
	rlwinm	r14, r14, 16, 16, 31	/* Get 16 msb */

	cmpwi	r14, CPU_TYPE_750
	beq	init_750
	cmpwi	r14, CPU_TYPE_7400
	beq	init_750
	cmpwi	r14, CPU_TYPE_750FX
	beq	init_750FX

	b	init_unknown_cpu
	
init_750FX:
	li	r1, 0x0
	mtspr	560, r1		/*	mtibatu	4, r1 */
	mtspr	561, r1		/*	mtibatl	4, r1 */
	mtspr	562, r1		/*	mtibatu	5, r1 */
	mtspr	563, r1		/*	mtibatl	5, r1 */
	mtspr	564, r1		/*	mtibatu	6, r1 */
	mtspr	565, r1		/*	mtibatl	6, r1 */
	mtspr	566, r1		/*	mtibatu	7, r1 */
	mtspr	567, r1		/*	mtibatl	7, r1 */
	mtspr	568, r1		/*	mtdbatu	4, r1 */
	mtspr	569, r1		/*	mtdbatl	4, r1 */
	mtspr	570, r1		/*	mtdbatu	5, r1 */
	mtspr	571, r1		/*	mtdbatl	5, r1 */
	mtspr	572, r1		/*	mtdbatu	6, r1 */
	mtspr	573, r1		/*	mtdbatl	6, r1 */
	mtspr	574, r1		/*	mtdbatu	7, r1 */
	mtspr	575, r1		/*	mtdbatl	7, r1 */
	isync
	sync

init_750:
	mfspr	r3, HID0
	lis	r4, 0xffff
	ori	r4, r4, 0x3fff
	and	r3, r3, r4
	sync
	isync
	mtspr	HID0, r3		/* Turn off L1 caches */
	sync
	isync

	li	r4, 0x0c00
	or	r3, r3, r4
	mtspr	HID0, r3		/* Clear L1 caches */

/* Set r16 to the load vs link offset. */

init_unknown_cpu:
	bl	1f
1:
	mflr	r3
	lis	r16, 0xffff
	and.	r16, r16, r3
	lis	r4, HI(start)
	sub	r16, r16, r4		/* R16 is now load offset */

/*
 *  Find out if executing in ROM or RAM.
 */

	lis	r15, 0x0400		/* 64MB default for ramloaded */
	lis	r4, 0xf000		/* Last 256Mb segment */
	and.	r4, r4, r3
	beq	in_ram			/* We are ram loaded! */

/*
 *  We are executing from ROM. We have to create the WORLD as we want it!
 *  Start by doing GT chip selects and SDRAM initilization.
 *
 *  WARNING!!! Relocating the GT chip in SMP mode is not safe!!!
 */
	lis	r5, HI(GT_BASE_ADDR_DEFAULT)
#if defined(SMP)
	ori	r4, r5, SMP_WHO_AM_I	/* Find out if SMP system and if CPU0 */
	lwbrx	r6, 0, (r4)
	cmpwi	r6, 0
	bne	not_cpu_0
#endif

	ori	r5, r5, INTERNAL_SPACE_BASE_ADDR
	lis	r6, HI(GT_BASE_ADDR >> 16)
	ori	r6, r6, LO(GT_BASE_ADDR >> 16)
	stwbrx	r6, 0, r5
        lis     r25, HI(GT_BASE_ADDR)
/**/
        GT_REGAD(CPU_CONFIG)		/*  CPU interface parameters, */
        lwbrx   r6, 0, (r5)		/*  change from default */

	ori	r6, r6, 0x2000		/* Pipeline enable */
	oris	r6, r6, 0x0002		/* Stop PCI retry... */

        stwbrx  r6, 0, (r5)
        sync
/**/
/* Set up device decoders to get them out of the way if reprogramming */
        GT_REGWR(DEVICE_BANK0_PARAMETERS, 0x8fefffff)
        GT_REGWR(DEVICE_BANK1_PARAMETERS, 0xcfcfffff)
        GT_REGWR(DEVICE_BANK2_PARAMETERS, 0xc0059bd7)

	GT_REGWR(DEV_CS0_BASE_ADDR, SRAM_BASE >> 16)
	GT_REGWR(DEV_CS0_SIZE, (SRAM_SIZE - 1) >> 16)
	GT_REGWR(DEV_CS1_BASE_ADDR, RTC_BASE >> 16)
	GT_REGWR(DEV_CS1_SIZE, (RTC_SIZE - 1) >> 16)
	GT_REGWR(DEV_CS2_BASE_ADDR, UART_BASE >> 16)
	GT_REGWR(DEV_CS2_SIZE, (UART_SIZE - 1) >> 16)

	li	r3, 7
	bl	dbglednum		/* CODE 111 - ALIVE */

/* Now we can start to print on serial console (if present) */
	PRINTSTR("\r\n\r\n\r\nPMON2000 PowerPC Initializing. Standby...\r\n")

	li	r3, 1
	bl	dbglednum		/* CODE 001 - Mapping setup */

	GT_REGWR(DEV_CS3_BASE_ADDR, FLASH_BASE >> 16)
	GT_REGWR(DEV_CS3_SIZE, (FLASH_SIZE - 1) >> 16)
	GT_REGWR(BOOTCS_SIZE, (BOOT_SIZE - 1) >> 16)
	GT_REGWR(BOOTCS_BASE_ADDR, BOOT_BASE >> 16)

        GT_REGAD(DEVICE_BOOT_BANK_PARAMETERS)	/* CS3 and BootCS width detection */
        lwbrx   r6,  0, r5
        andis.  r6, r6, 0x0030
        cmpwi   r6, 0x0
        bne     boot_32_bit

	DBGPRINTSTR("Boot 8 bit\r\n")

        GT_REGWR(DEVICE_BANK3_PARAMETERS, 0xc4a82f1f)
        GT_REGWR(DEVICE_BOOT_BANK_PARAMETERS, 0xc00b5e7f)

        b       cont_init

boot_32_bit:
	DBGPRINTSTR("Boot 32 bit\r\n")

        GT_REGWR(DEVICE_BANK3_PARAMETERS, 0xc00b5e7f)
        GT_REGWR(DEVICE_BOOT_BANK_PARAMETERS, 0xc4a82f1f)

cont_init:
	xor	r0, r0, r0

/*
 *  Configure SDRAM. Use SPD data to figure out module size and config.
 */
	bl	boot_i2c_init		/* Yep, initialize the I2C interface */
	li	r3, 2
	bl	dbglednum		/* CODE 010 - Memory module probing */

	DBGPRINTSTR("Probing MAIN SDRAM module\r\n")
	li	r3, 0x600
	bl	probe_sdram_size	/* Probe MAIN SDRAM module */
	or	r17, r3, r3

	DBGPRINTSTR("Probing SECONDARY SDRAM module\r\n")
	li	r3, 0x400
	bl	probe_sdram_size	/* Probe SECONDARY SDRAM module */
	or	r18, r3, r3

	add.	r15, r17, r18		/* Compute total memory size */
	beq	bootinit_nomem		/* no module found */

	cmpwi	r17, 0x0
	beq	useslot2param
	li	r3, 0x603		/* Get number of rows */
	bl	boot_i2c_read
	or	r12, r3, r3
	li	r3, 0x612		/* Get cas latency */
	bl	boot_i2c_read
	or	r13, r3, r3
	li	r3, 0x615		/* Get module type */
	bl	boot_i2c_read
	or	r11, r3, r3
	b	useslot1param

useslot2param:
	li	r3, 0x403		/* Get number of rows */
	bl	boot_i2c_read
	or	r12, r3, r3
	li	r3, 0x412		/* Get cas latencty */
	bl	boot_i2c_read
	or	r13, r3, r3
	li	r3, 0x415		/* Get module type */
	bl	boot_i2c_read
	or	r11, r3, r3

useslot1param:
	andi.	r11, r11, 0x2
	li	r3, 3
	bl	dbglednum

/*
 *  Note! r11 = 0 if nonregistred. r12 = rowadr size. r13 = cas latencey.
 *  This code assumes that both memory modules (if two are used) are
 *  of the same type, size and speed.
 */
	GT_REGAD(SRAM_DATA0)
	li	r7, 64
	mtctr	r7
	li	r7, 0x41
	li	r8, 0
1:
	stwbrx	r8, 0, (r5)
	eieio;sync
	add	r8, r8, r7
	bdnz	1b

	GT_REGWR(DFCDL_CONFIG0, 0x00300000)
/**/
	GT_REGWR(SDRAM_OPERATION, 5)		/* Send a nop */
1:
	lwbrx	r6, 0, (r5)
	andi.	r6, r6, 0x7
	bne	1b				/* Wait for idle */

/*  Check if module is registred or not and set up accordingly */
	cmpwi	r11, 0x0			/* Registred? */
	beq	sdram_set_nonreg

	DBGPRINTSTR("SDRAM Registred\r\n")
        GT_REGWR(SDRAM_CONFIG, 0x58220400)	/* Set registered */
	b	sdram_set_mode

sdram_set_nonreg:
	DBGPRINTSTR("SDRAM Nonregistred\r\n")
        GT_REGWR(SDRAM_CONFIG, 0x58200400)	/* Set nonregistred */

/**/
sdram_set_mode:
	GT_REGWR(SDRAM_OPEN_PAGES_CONTROL, 0)	/* Keep pages open */

/* Set up CAS latency. r13 = cas latency register. */
/* 0x02000001 / 0x00000052  CL 1.5  */
/* 0x23000001 / 0x00000052  CL 1.5s */
/* 0x03000001 / 0x00000052  CL 1.5r */
/* 0x23000002 / 0x00000022  CL 2.0  */
/* 0x03000002 / 0x00000022  CL 2.0s */
/* 0x24000002 / 0x00000022  CL 2.0r */
/* 0x03000003 / 0x00000062  CL 2.5  */
/* 0x24000003 / 0x00000062  CL 2.5  */
/* 0x04000003 / 0x00000062  CL 2.5r */
/* 0x24000004 / 0x00000032  CL 3.0  */
/* 0x24000004 / 0x00000032  CL 3.0s */
/* 0x25000004 / 0x00000032  CL 3.0r */

	GT_REGAD(D_UNIT_CONTROL_LOW)
	lwbrx	r9,0, (r5)
	andi.	r9, r9, 1			/* r9 = synchronous status */

	srwi	r13, r13, 0x1
	cmpwi	r13, 0x0001
	beq	cas1				/* CAS 1 */
	srwi	r13, r13, 0x1
	cmpwi	r13, 0x0001
	beq	cas2				/* CAS 2 */
	srwi	r13, r13, 0x1
	cmpwi	r13, 0x0001
	beq	cas3				/* CAS 3 */
	b	cas4				/* CAS 4 */

cas1:
	lis	r8, 0x0300
	li	r7, 0x0052
	cmpwi	r11, 0x0
	bne	settiming
	lis	r8, 0x0200
	cmpwi	r9, 1
	bne	settiming
	lis	r8, 0x2300
	b	settiming

cas2:
	lis	r8, 0x2400
	li	r7, 0x0022
	cmpwi	r11, 0x0
	bne	settiming
	lis	r8, 0x2300
	cmpwi	r9, 1
	bne	settiming
	lis	r8, 0x0300
	b	settiming
	
cas3:
	lis	r8, 0x0400
	li	r7, 0x0062
	andi.	r0, r11, 0x2
	bne	settiming
	lis	r8, 0x0300
	cmpwi	r9, 1
	bne	settiming
	lis	r8, 0x2400
	b	settiming

cas4:
	lis	r8, 0x2500