start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	srl	t1, t3, 9
	and	t1, 3
	sllv	s3, t2, t1		/* s3 = I cache size */

	and	t1, t3, 0x20
	srl	t1, t1, 1
	addu	s4, t1, 16		/* s4 = I cache line size */

	srl	t1, t3, 6
	and	t1, 3
	sllv	s5, t2, t1		/* s5 = D cache size */

	and	t1, t3, 0x10
	addu	s6, t1, 16		/* s6 = D cache line size */

	and	t1, t3, CF_7_TC
	bnez	t1, Conf7KL2		/* Any L3 disabled if set */
	li	s8, 0

	la	v0, PLD_BASE_ADDR
	lb	t0, BOARD_STAT(v0)
	and	t0, t0, BOARD_L3_MASK

	beq	t0, zero, Conf7KL2
	li	t1, BOARD_L3_2MB

	li	s8, 1024 * 1024 * 2
	beq	t0, t1, Conf7KL2
	li	t1, BOARD_L3_4MB

	li	s8, 1024 * 1024 * 4
	beq	t0, t1, Conf7KL2
	li	t1, BOARD_L3_8MB

	li	s8, 1024 * 1024 * 8
#if 0
	li	t0, CF_7_TS		/* Use when cache size is in cfg reg */
	and	t1, t3, t0
	beq	t1, t0, Conf7KL2
	srl	t1, CF_7_TS_AL

	li	s8, 5024288		/* 512k */
	sll	s8, t1
#endif

Conf7KL2:
#if defined(NO_L3_CACHE)
	li	s8, 0			/* Don't use any L3 cache! */
#endif
	and	t1, t3, CF_7_SC
	bnez	t1, Conf7KEnd
	li	s7, 0

	li	s7, 262144

Conf7KEnd:

/*
 *  Clear out 8Mb of memory (maximum cache size)
 */

	TTYDBG("Clearing cache size memory...\r\n");

	la	t0, UNCACHED_MEMORY_ADDR+0x800000
	addu	t1, t0, 8*1024*1024
1:
	addu	t0, 8
	bne	t1, t0, 1b
	sd	zero, -8(t0)

	TTYDBG("Disable cache exceptions...\r\n");

	mfc0	t0, COP_0_STATUS_REG
	and	t1, t0, SR_BOOT_EXC_VEC
	or	t1, SR_DIAG_DE
	mtc0	t1, COP_0_STATUS_REG

	mtc0	zero, COP_0_TAG_LO
	mtc0	zero, COP_0_TAG_HI
	mtc0	zero, COP_0_ECC

	and	t2, t3, ~(CF_7_SE|CF_7_TE)
	mtc0	t2, COP_0_CONFIG		/* Disable L2 and L3 */
	NOP8

/*
 *  Do L1 instruction cache.
 */

	TTYDBG("Init L1 instruction cache...\r\n")

	la	a0, CACHED_MEMORY_ADDR+0x800000
	addu	a1, a0, s3			/* End = size of I cache */

1:
	addu	a0, s4				/* Step by line size */
	cache	IndexStoreTagI, -4(a0)
	nop
	cache	FillI, -4(a0)
	nop
	bne	a0, a1, 1b
	cache	IndexStoreTagI, -4(a0)

/*
 *  Do L1 data cache.
 */

	TTYDBG("Init L1 data cache...\r\n")

	la	a0, CACHED_MEMORY_ADDR+0x800000
	add	a1, a0, s5			/* End = size of D cache */

1:
	addu	a0, s6				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagD, -4(a0)

	la	a0, CACHED_MEMORY_ADDR+0x800000
	add	a1, a0, s5			/* End = size of D cache */

1:
	addu	a0, s6				/* Step by line size */
	bne	a0, a1, 1b
	lw	zero, -4(a0)

	la	a0, CACHED_MEMORY_ADDR+0x800000
	add	a1, a0, s5			/* End = size of D cache */

1:
	addu	a0, s6				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagD, -4(a0)

	beqz	s7, no_L2_cache
	nop

/*
 *  Do L2 cache
 */

	TTYDBG("Init L2 unified cache...\r\n")

	or	t3, CF_7_SE			/* Enable secondary cache */
	mtc0	t3, COP_0_CONFIG
	NOP8

	la	a0, CACHED_MEMORY_ADDR+0x800000
	add	a1, a0, s7			/* End = size of L2 cache */

1:
	addu	a0, 32				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagS, -4(a0)

	sync

	la	a0, CACHED_MEMORY_ADDR+0x800000
	add	a1, a0, s7			/* End = size of L2 cache */

1:
	addu	a0, 32				/* Step by line size */
	bne	a0, a1, 1b
	lw	zero, -4(a0)

	sync

	la	a0, CACHED_MEMORY_ADDR+0x800000
	add	a1, a0, s7			/* End = size of L2 cache */

1:
	addu	a0, 32				/* Step by line size */
	bne	a0, a1, 1b
	cache	IndexStoreTagS, -4(a0)

	sync

no_L2_cache:

/*
 *  Do any L3 cache
 */

	beqz	s8, no_L3_cache			/* Any L3 size? */
	nop

	TTYDBG("Init L3 unified cache...\r\n")

	or	t3, CF_7_TE			/* Enable tertiary cache */
	mtc0	t3, COP_0_CONFIG
	NOP8

	mtc0	zero, COP_0_TAG_HI
	mtc0	zero, COP_0_TAG_LO

	la	a0, CACHED_MEMORY_ADDR+0x800000
	addu	a1, a0, s8			/* Compute size of L3 */

1:
#	cache   InvalidateTertiaryPage, 0(a0)
	addu	a0, 128*32
#	cache	IndexStoreTagT, 0(a0)
#	addu	a0, 32
	bne	a0, a1, 1b
	nop

no_L3_cache:

/**/
	mtc0	t0, COP_0_STATUS_REG		/* Restore status reg */
	mtc0	t3, COP_0_CONFIG		/* Restore cache config */
	NOP8

	TTYDBG("Init caches done!\r\n")

/*
 *  At this point all memory controller setup should have been done
 *  and we should be able to function 'normally' and C code can be
 *  used freely from this point.
 */

#ifdef DRAM_MEM_TEST
#define MEM_TEST_START	(CACHED_MEMORY_ADDR+0x00000000)
#define MEM_TEST_END	(CACHED_MEMORY_ADDR+0x08000000)
#ifdef MEM_SETUP_ALL
	TTYDBG("Writing RAMP to 128MB of Memory ...")
	la	t0, MEM_TEST_START
	la	t1, MEM_TEST_END
#else
	TTYDBG("Writing RAMP to 8MB of Memory ...")
	la	t0, MEM_TEST_START
	la	t1, MEM_TEST_END
#endif
1:
	sw	t0, 0(t0)
	daddiu	t0, 4	
	bne	t0, t1, 1b
	nop
	TTYDBG("Done\r\n")

#ifdef MEM_SETUP_ALL
	TTYDBG("Reading back 128MB of Memory ...")
	la	t0, MEM_TEST_START
	la	t1, MEM_TEST_END
#else
	TTYDBG("Reading back 8MB of Memory ...")
	la	t0, MEM_TEST_START
	la	t1, MEM_TEST_END
#endif
1:
	lw	t2, 0(t0)
	nop
	bne	t0, t2, 3f
	daddiu	t0, 4
2:
	bne	t0, t1, 1b
	nop
	TTYDBG("Done\r\n")
	b	4f
	nop
3:
	TTYDBG("Failed at ")
	add	a0, t0, -4
	bal	hexserial
	nop
	TTYDBG(", got ")
	move	a0, t2
	bal	hexserial
	nop
	TTYDBG("\r\n")
	TTYDBG("Skip to next MB boundary\r\n")
	srl	t0, 20
	daddiu	t0, 1
	sll	t0, 20
	b	2b
	nop
4:

#ifdef MEM_SETUP_ALL
	TTYDBG("Writing Reverse RAMP to 128MB of Memory ...")
	la	t0, MEM_TEST_START
	la	t1, MEM_TEST_END
#else
	TTYDBG("Writing Reverse RAMP to 8MB of Memory ...")
	la	t0, MEM_TEST_START
	la	t1, MEM_TEST_END
#endif
1:
	move	t2, t0
	not	t2
	sw	t2, 0(t0)
	daddiu	t0, 4	
	bne	t0, t1, 1b
	nop
	TTYDBG("Done\r\n")

#ifdef MEM_SETUP_ALL
	TTYDBG("Reading back 128MB of Memory ...")
	la	t0, MEM_TEST_START
	la	t1, MEM_TEST_END
#else
	TTYDBG("Reading back 8MB of Memory ...")
	la	t0, MEM_TEST_START
	la	t1, MEM_TEST_END
#endif
1:
	lw	t2, 0(t0)
	nop
	not	t2
	bne	t0, t2, 3f
	daddiu	t0, 4
2:
	bne	t0, t1, 1b
	nop
	TTYDBG("Done\r\n")
	b	4f
	nop
3:
	TTYDBG("Failed at ")
	add	a0, t0, -4
	bal	hexserial
	nop
	TTYDBG(", got ")
	move	a0, t2
	bal	hexserial
	nop
	TTYDBG("\r\n")
	TTYDBG("Skip to next MB boundary\r\n")
	srl	t0, 20
	daddiu	t0, 1
	sll	t0, 20
	b 	2b
	nop
4:
#ifdef DRAM_MEM_TEST_FOREVER
	b	in_ram
	nop
#endif
#endif

	TTYDBG("Copy PMON to execute location...\r\n")
#ifdef DEBUG_LOCORE
	TTYDBG("start = ")
	la	a0, start
	bal	hexserial
	nop
	TTYDBG("\r\ncopytoram = ")
	la	a0, copytoram
	addu	a0, s0
	bal	hexserial
	nop
	TTYDBG("\r\ns0 = ")
	move	a0, s0
	bal	hexserial
	nop
	TTYDBG("\r\n")
#endif

	la	a1, start	/* RAM start address */
	la	v0, copytoram
	addu	v0, s0		/* Compute ROM address of 'copytoram' */
	jal	v0
	add	a0, a1, s0	/* ROM start address */

	beqz	v0, 1f
	nop

	la	a0, copyfail_msg
	bal	stringserial
	nop
	b	stuck
	nop

1:
	TTYDBG("Copy PMON to execute location done.\r\n")

	sw	s8, CpuTertiaryCacheSize /* Set L3 cache size */

	lw	a0, 0x810(s2)		/* get stuffed away memory size data */
	lw	a1, 0x810(s2)	
	la	v0, initmips
	jalr	v0
	nop

stuck:
	b	stuck
	nop



/*
 * Simple character printing routine used before full initialization
 */

LEAF(stringserial)
	move	a2, ra
	addu	a1, a0, s0
	lbu	a0, 0(a1)
1:
	beqz	a0, 2f
	nop
	bal	tgt_putchar
	addiu	a1, 1
	b	1b
	lbu	a0, 0(a1)

2:
	j	a2
	nop
END(stringserial)

LEAF(hexserial)
	move	a2, ra
	move	a1, a0
	li	a3, 7
1:
	rol	a0, a1, 4
	move	a1, a0
	and	a0, 0xf
	la	v0, hexchar
	addu	v0, s0
	addu	v0, a0
	bal	tgt_putchar
	lbu	a0, 0(v0)

	bnez	a3, 1b
	addu	a3, -1

	j	a2
	nop
END(hexserial)
	

LEAF(tgt_putchar)
	la	v0, COM1_BASE_ADDR
1:
	lbu	v1, NSREG(NS16550_LSR)(v0)
	and	v1, LSR_TXRDY
	beqz	v1, 1b
	nop

	sb	a0, NSREG(NS16550_DATA)(v0)
	j	ra
	nop	
END(tgt_putchar)

/* baud rate definitions, matching include/termios.h */
#define B0      0
#define B50     50      
#define B75     75
#define B110    110
#define B134    134
#define B150    150
#define B200    200
#define B300    300
#define B600    600
#define B1200   1200
#define B1800   1800
#define B2400   2400
#define B4800   4800
#define B9600   9600
#define B19200  19200
#define B38400  38400
#define B57600  57600
#define B115200 115200

LEAF(initserial)
	la	v0, COM1_BASE_ADDR
1:
	li	v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
	sb	v1, NSREG(NS16550_FIFO)(v0)
	li	v1, CFCR_DLAB
	sb	v1, NSREG(NS16550_CFCR)(v0)
	li	v1, NS16550HZ/(16*CONS_BAUD)
	sb	v1, NSREG(NS16550_DATA)(v0)
	srl	v1, 8
	sb	v1, NSREG(NS16550_IER)(v0)
	li	v1, CFCR_8BITS
	sb	v1, NSREG(NS16550_CFCR)(v0)
#if 0
	li	v1, MCR_DTR|MCR_RTS
#endif
	sb	v1, NSREG(NS16550_MCR)(v0)
	li	v1, 0x0
	sb	v1, NSREG(NS16550_IER)(v0)

	move	v1, v0
	la	v0, COM2_BASE_ADDR
	bne	v0, v1, 1b
	nop

	j	ra
	nop
END(initserial)

/*
 *  Clear the TLB. Normally called from start.S.
 */
LEAF(CPU_TLBClear)
	li	a3, 0			# First TLB index.

	li	a2, PG_SIZE_4K
	dmtc0   a2, COP_0_TLB_PG_MASK   # Whatever...

1:
	dmtc0   zero, COP_0_TLB_HI	# Clear entry high.
	dmtc0   zero, COP_0_TLB_LO0	# Clear entry low0.
	dmtc0   zero, COP_0_TLB_LO1	# Clear entry low1.

	mtc0    a3, COP_0_TLB_INDEX	# Set the index.
	addiu	a3, 1
	li	a2, 64
	nop
	nop
	tlbwi				# Write the TLB

	bne	a3, a2, 1b
	nop

	jr	ra
	nop
END(CPU_TLBClear)

/*
 *  Set up the TLB. Normally called from start.S.
 */
LEAF(CPU_TLBInit)
	li	a3, 0			# First TLB index.

	li	a2, PG_SIZE_16M
	dmtc0   a2, COP_0_TLB_PG_MASK   # All pages are 16Mb.

1:
	and	a2, a0, PG_SVPN
	dmtc0   a2, COP_0_TLB_HI	# Set up entry high.

	move	a2, a0
	srl	a2, a0, PG_SHIFT 
	and	a2, a2, PG_FRAME
	ori	a2, PG_IOPAGE
	dmtc0   a2, COP_0_TLB_LO0	# Set up entry low0.
	addu	a2, (0x01000000 >> PG_SHIFT)
	dmtc0   a2, COP_0_TLB_LO1	# Set up entry low1.

	mtc0    a3, COP_0_TLB_INDEX	# Set the index.
	addiu	a3, 1
	li	a2, 0x02000000
	subu	a1, a2
	nop
	tlbwi				# Write the TLB

	bgtz	a1, 1b
	addu	a0, a2			# Step address 32Mb.

	jr	ra
	nop
END(CPU_TLBInit)

__main:
	j	ra
	nop


	.rdata
copyfail_msg:
	.asciz	"\r\nPANIC! Copy to memory failed!\r\n"
transmit_pat_msg:
	.asciz	"\r\nInvalid transmit pattern.  Must be DDDD or DDxDDx\r\n"
v200_msg:
	.asciz	"\r\nPANIC! Unexpected TLB refill exception!\r\n"
v280_msg:
	.asciz	"\r\nPANIC! Unexpected XTLB refill exception!\r\n"
v380_msg:
	.asciz	"\r\nPANIC! Unexpected General exception!\r\n"
v400_msg:
	.asciz	"\r\nPANIC! Unexpected Interrupt exception!\r\n"
hexchar:
	.ascii	"0123456789abcdef"