ck3.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: ck3.h,v 1.6 2003/03/24 13:05:48 pefo Exp $ */

/*
 * Copyright (c) 2000 Opsycon AB  (www.opsycon.se)
 * Copyright (c) 2000 Rtmx, Inc   (www.rtmx.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for Rtmx, Inc by
 *	Opsycon Open System Consulting AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _K2_H_
#define _K2_H_

#include <pmon/dev/cpc710.h>

/*
 *  PCI Bus allocation
 */
#define CPU_PCI32_ISA_IO_ADRS   0x80000000      /* base addr of PCI/ISA/IO */
#define CPU_PCI32_ISA_IO_SIZE   0x00010000      /* 64 K */
#define CPU_PCI32_ISA_MEM_ADRS  0xc0000000      /* base of PCI mem address */
#define CPU_PCI32_ISA_MEM_SIZE  0x01000000      /* 16 M */ 

/* We are using PCI32 to map ISA addresses */
#define CPU_PCI_ISA_IO_ADRS     CPU_PCI32_ISA_IO_ADRS
#define CPU_PCI_ISA_IO_SIZE     CPU_PCI32_ISA_IO_SIZE
#define CPU_PCI_ISA_MEM_ADRS    CPU_PCI32_ISA_MEM_ADRS
#define CPU_PCI_ISA_MEM_SIZE    CPU_PCI32_ISA_MEM_SIZE

/* IO and MEM space */
#define CPU_PCI32_IO_ADRS       (CPU_PCI32_ISA_IO_ADRS + 0x01000000)
#define CPU_PCI32_IO_SIZE       0x01000000 /* (CPU_PCI32_ISA_IO_SIZE - 0x0100000
0)*/
#define CPU_PCI32_MEM_ADRS      (CPU_PCI32_ISA_MEM_ADRS + 0x01000000)
#define CPU_PCI32_MEM_SIZE      0x10000000 /* (CPU_PCI32_ISA_MEM_SIZE - 0x010000
00) */

/* we are using PCI32 for PCI IO and MEM accessess */
#define CPU_PCI_IO_ADRS         CPU_PCI32_IO_ADRS
#define CPU_PCI_IO_SIZE         CPU_PCI32_IO_SIZE
#define CPU_PCI_MEM_ADRS        CPU_PCI32_MEM_ADRS
#define CPU_PCI_MEM_SIZE        CPU_PCI32_MEM_SIZE

#define CPU_PCI64_IO_ADRS       0x90000000
#define CPU_PCI64_IO_SIZE       0x04000000      /* 64 M */
#define CPU_PCI64_MEM_ADRS      0xa0000000
#define CPU_PCI64_MEM_SIZE      0x20000000      /* 512M */ 

/* ISA accessess */
#define PCI32_ISA_IO_ADRS       0x00000000      /* base of PCI I/O address */
#define PCI32_ISA_IO_SIZE       0x04000000      /* 64 M */
#define PCI32_ISA_MEM_ADRS      0x00000000      /* changed from 0x4000000 */
#define PCI32_ISA_MEM_SIZE      0x10000000      /* 256 M */

/* We are using PCI32 to map ISA space */
#define PCI_ISA_IO_ADRS         PCI32_ISA_IO_ADRS
#define PCI_ISA_IO_SIZE         PCI32_ISA_IO_SIZE
#define PCI_ISA_MEM_ADRS        PCI32_ISA_MEM_ADRS
#define PCI_ISA_MEM_SIZE        PCI32_ISA_MEM_SIZE

/* PCI IO and MEM accessess */
#define PCI32_IO_ADRS           (PCI32_ISA_IO_ADRS + 0x01000000)
#define PCI32_IO_SIZE           0x00010000 /* (PCI32_ISA_IO_SIZE - 0x01000000) */
#define PCI32_MEM_ADRS          (PCI32_ISA_MEM_ADRS + 0x01000000)
#define PCI32_MEM_SIZE          0x10000000 /* (PCI32_ISA_MEM_SIZE - 0x01000000)*/ 
#define PCI64_IO_ADRS           0x00000000
#define PCI64_IO_SIZE           0x40000000      /* 1 G */
#define PCI64_MEM_ADRS          0x40000000
#define PCI64_MEM_SIZE          0x10000000      /* 256 M */

#define	PCI_MEM_SPACE_BASE	0xc0000000
#define	PCI_MEM_SPACE_SIZE	(0xf8000000-PCI_MEM_SPACE_BASE)
#define	PCI_IO_SPACE_BASE	0x80000000
#define	PCI_IO_SPACE_SIZE	(0xfc000000-PCI_IO_SPACE_BASE)

/* Size values for CPC710 */
#define PCI32_IOSIZE            0xfc000000      /* 64 M */
#define PCI32_MEMSIZE           0xf0000000      /*  1 G */
#define PCI64_IOSIZE            PCI32_IOSIZE    /* 64 M */
#define PCI64_MEMSIZE           PCI32_MEMSIZE   /*  1 G */ 

/*
 *  NV-Ram.
 */
#define NVRAM_SIZE		0x7fe0	/* How many bytes, clock cells excl. */
#define NVRAM_BASE		(PCI_MEM_SPACE_BASE + 0x90000)
#define	NVRAM_FIRST_ENV		(NVRAM_BASE + 0x0000)
#define	NVRAM_LAST_ENV		(NVRAM_BASE + 0x3fff)
#define	NVRAM_SIZE_ENV		(NVRAM_LAST_ENV - NVRAM_FIRST_ENV + 1)
#define	NVRAM_VXWORKS		(NVRAM_BASE + NVRAM_SIZE - 512 + 16)
#define	NVRAM_VXWORKS_DEFAULT \
"dc(0,0)host:/usr/vw/config/powerk2/vxWorks h=90.0.0.3 e=90.0.0.50 u=target"

#define M48T18_BASE		(NVRAM_BASE + 0x7ff8)

/*
 *  I/O ports.
 */
#define COM1_BASE_ADDR		(PCI_IO_SPACE_BASE + 0x3f8)	/* Com 1 */
#define COM2_BASE_ADDR		(PCI_IO_SPACE_BASE + 0x2f8)	/* Com 2 */
#define	NS16550HZ		1843200

#define	K2_CNTL_REG		(PCI_IO_SPACE_BASE + 0x804)
#define	K2_HOT_SWAP		(PCI_IO_SPACE_BASE + 0x80c)
#define	K3_FLASH_PAGE		(PCI_IO_SPACE_BASE + 0x80d)
#define K2_WD_ENABLE		(NVRAM_BASE + 0x7ff7)


#endif