📄 tgt_machdep.c
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/* $Id: tgt_machdep.c,v 1.8 2003/01/30 14:54:39 pefo Exp $ *//* * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) * Copyright (c) 2000 Rtmx, Inc (www.rtmx.com) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for Rtmx, Inc by * Opsycon Open System Consulting AB, Sweden. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */#include <sys/types.h>#include <stdio.h>#include <termio.h>#include <string.h>#include <time.h>#include <sys/device.h>#include <dev/pci/pcivar.h>#include <machine/cpu.h>#include <machine/pio.h>#include <machine/asm.h>#include <machine/inline_asm.h>#include <autoconf.h>#include "pflash.h"#include "dev/pflash_tgt.h"#include "target/ck3.h"#include <pmon.h>#include <pmon/netio/netio.h>#include <pmon/dev/ns16550.h>extern unsigned char hwethadr[6];static int md_pipefreq = 0;static int md_cpufreq = 0;static int clk_invalid = 0;static int nvram_invalid = 0;ConfigEntry ConfigTable[] ={ { (char *)COM1_BASE_ADDR, 0, ns16550, 256, CONS_BAUD, NS16550HZ}, { (char *)COM2_BASE_ADDR, 0, ns16550, 256, CONS_BAUD, NS16550HZ}, { 0 }};unsigned long _filebase;static void _probe_frequencies __P((void));static int cksum __P((void *, size_t, int));/* * Target dependent version printout. * Printout available target version information. */voidtgt_cmd_vers(){}/* * This function makes inital HW setup for debugger and * returns the apropriate setting for the status register. */register_ttgt_enable(int machtype){ /* XXX Do any HW specific setup */ return(PSL_IR|PSL_DR|PSL_FP|PSL_RI|PSL_ME|PSL_FE_DFLT);}voidtgt_logo(){}voidtgt_rtinit(){}static void_probe_frequencies(){ int i, timeout, sec, cur, cnt; int clkbase = M48T18_BASE; SBD_DISPLAY ("FREQ", CHKPNT_FREQ); md_pipefreq = 300000000; /* Defaults */ md_cpufreq = 100000000; /* * Check if clock is stopped and start it if it is. */ if(inb(clkbase + 1) & 0x80) { outb(clkbase + 1, inb(clkbase + 1) & 0x7f); clk_invalid = 1; } /* * Do the next twice for two reasons. First make sure we run from * cache. Second make sure synched on second update. (Pun intended!) */ for(i = 2; i != 0; i--) { cnt = get_count(); timeout = 10000000; outb(clkbase, inb(clkbase) | 0x40); /* stop update */ sec = inb(clkbase + 1) & 0x0f; outb(clkbase, inb(clkbase) & ~0x40); /* start update */ do { timeout--; outb(clkbase, inb(clkbase) | 0x40); cur = inb(clkbase + 1) & 0x0f; outb(clkbase, inb(clkbase) & ~0x40); } while(timeout != 0 && cur == sec); cnt = get_count() - cnt; if(timeout == 0) { clk_invalid = 1; return; /* Get out if clock is not running */ } } /* * Calculate the cpu pipeline frequency. */ md_cpufreq = (cnt + 50000) / 100000; md_cpufreq *= 400000; md_pipefreq = md_getpipefreq(md_cpufreq);}/* * Returns the CPU pipelie clock frequency */inttgt_pipefreq(){ if(md_pipefreq == 0) { _probe_frequencies(); } return(md_pipefreq);}/* * Returns the external clock frequency, usually the bus clock */inttgt_cpufreq(){ if(md_cpufreq == 0) { _probe_frequencies(); } return(md_cpufreq);}#ifdef HAVE_TOD/* * Returns the current time if a TOD clock is present or 0 * This code is defunct after 2088... (out of bits) */#define FROMBCD(x) (((x) >> 4) * 10 + ((x) & 0xf))#define TOBCD(x) (((x) / 10 * 16) + ((x) % 10)) #define YEARDAYS(year) ((((year) % 4) == 0 && \ ((year % 100) != 0 || (year % 400) == 0)) ? 366 : 365)#define SECMIN (60) /* seconds per minute */#define SECHOUR (60*SECMIN) /* seconds per hour */#define SECDAY (24*SECHOUR) /* seconds per day */#define SECYR (365*SECDAY) /* seconds per common year */static const short dayyr[12] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 };time_ttgt_gettime(){ struct tm tm; int clkbase = M48T18_BASE; time_t t; outb(clkbase, inb(clkbase) | 0x40); tm.tm_sec = FROMBCD(inb(clkbase + 1)); tm.tm_min = FROMBCD(inb(clkbase + 2)); tm.tm_hour = FROMBCD(inb(clkbase + 3)); tm.tm_wday = FROMBCD(inb(clkbase + 4)); tm.tm_mday = FROMBCD(inb(clkbase + 5)); tm.tm_mon = FROMBCD(inb(clkbase + 6)) - 1; tm.tm_year = FROMBCD(inb(clkbase + 7)); outb(clkbase, inb(clkbase) & ~0x40); tm.tm_isdst = tm.tm_gmtoff = 0; if(tm.tm_year < 90) { tm.tm_year += 100; } t = gmmktime(&tm); return(t);}/* * Set the current time if a TOD clock is present */voidtgt_settime(time_t t){ struct tm *tm; int clkbase = M48T18_BASE; tm = gmtime(&t); /* Enable register writing */ outb(clkbase, inb(clkbase) | 0x80); outb(clkbase + 7, TOBCD(tm->tm_year % 100)); outb(clkbase + 6, TOBCD(tm->tm_mon + 1)); outb(clkbase + 5, TOBCD(tm->tm_mday)); outb(clkbase + 4, TOBCD(tm->tm_wday)); outb(clkbase + 3, TOBCD(tm->tm_hour)); outb(clkbase + 2, TOBCD(tm->tm_min)); outb(clkbase + 1, TOBCD(tm->tm_sec)); /* Transfer new time to counters */ outb(clkbase, inb(clkbase) & ~0x80);}#endif /* HAVE_TOD *//* * Print out any target specific memory information */voidtgt_memprint(){}voidtgt_machprint(){ printf("BSP Copyright 2001-2003, SBS Technologies, Inc.\n"); printf("CPU PowerPC %s @", md_cpuname());} /* * Return a suitable address for the client stack. * Usually top of RAM memory. */register_ttgt_clienttos(){ return((memorysize & ~7) - 64);}/* * Flash programming support code. *//* * Table of flash devices on target. See pflash_tgt.h. */struct fl_map tgt_fl_map[] = { TARGET_FLASH_DEVICES};struct fl_map tgt_fl_map_intel[] = { TARGET_FLASH_DEVICES_INTEL};voidtgt_flashinit(){}struct fl_map *tgt_flashmap(){ /* Configure selects if not done */ if((in32(CPC710_GPDIR) & 0xc0000000) != 0xc0000000) { out32(CPC710_GPDIR, 0xc0000000); out32(CPC710_GPOUT, 0x80000000); out8(K3_FLASH_PAGE, 0); } if((in32(CPC710_GPOUT) & 0x80000000) == 0) { return(tgt_fl_map_intel); } else { return(tgt_fl_map); }}voidtgt_flashwrite_disable(){ out32(CPC710_UCTL, in32(CPC710_UCTL) | ~0xf7ffffff);}inttgt_flashwrite_enable(){ out32(CPC710_UCTL, in32(CPC710_UCTL) & 0xf7ffffff); return(1);}/* * Page select. * * If page is < 0 - Map in AMD but leave intel page as is. * If page is >= 0 - Map out AMD and select intel page. */inttgt_flashsetpageno(int page){ if (page < 0) { out32(CPC710_GPDIR, 0xc0000000); out32(CPC710_GPOUT, 0x80000000); return(0); } else if (page <= 15) { out32(CPC710_GPDIR, 0xc0000000); out32(CPC710_GPOUT, 0x00000000); out8(K3_FLASH_PAGE, page); return(0); } return(-1);}voidtgt_flashinfo(void *p, size_t *t){ struct fl_map *map; map = fl_find_map(p); if(map) { *t = map->fl_map_size; } else { *t = 0; }}voidtgt_flashprogram(void *p, int size, void *s, int endian){ printf("Programming flash %p:%p into %p\n", s, size, p); if(fl_erase_device(p, size, TRUE)) { printf("Erase failed!\n"); return; } if(fl_program_device(p, s, size, TRUE)) { printf("Programming failed!\n"); } fl_verify_device(p, s, size, TRUE);}/* * Network stuff. */voidtgt_netinit(){}inttgt_ethaddr(char *p){ bcopy((void *)&hwethadr, p, 6); return(0);}voidtgt_netreset(){}/* * --- NVRAM handling code --- *//* * Special copy that does it bytewise, guaranteed! */static void bytecopy __P((char *, char *, size_t));staticvoid bytecopy(char *src, char *dst, size_t size){ if(src == NULL) { *dst = '\0'; } else if (dst >= src && dst < src + size) { src += size; dst += size; while (size--) { *--dst = *--src; } } else while (size--) { *dst++ = *src++; }}/* * Read in environment from NV-ram and set. */voidtgt_mapenv(int (*func) __P((char *, char *))){ char *ep; char env[256]; /* * Check integrity of the NVRAM env area. If not in order * initialize it to empty. */ if(cksum((void *)NVRAM_FIRST_ENV, NVRAM_SIZE_ENV, 0) != 0) { nvram_invalid = 1; } else { ep = (char *)NVRAM_FIRST_ENV + 2; while(*ep != 0) { char *val = 0, *p = env; while((*p++ = *ep++) != 0 && (ep < (char *)NVRAM_LAST_ENV)) { if((*(p - 1) == '=') && (val == NULL)) { *(p - 1) = '\0'; val = p; } } if(ep < (char *)NVRAM_LAST_ENV) { (*func)(env, val); } else { nvram_invalid = 2; break; } } bytecopy((char *)NVRAM_VXWORKS, env, sizeof(env)); (*func)("vxWorks", env); } sprintf(env, "%d", memorysize / (1024 * 1024)); (*func)("memsize", env); sprintf(env, "%d", md_pipefreq); (*func)("cpuclock", env); sprintf(env, "%d", md_cpufreq); (*func)("busclock", env); (*func)("systype", "ck3");}inttgt_unsetenv(char *name){ char *ep; char *np; char *sp; if(nvram_invalid) { return(0); } ep = (char *)NVRAM_FIRST_ENV + 2; while((*ep != '\0') && (ep < (char *)NVRAM_LAST_ENV)) { np = name; sp = ep; while((*ep == *np) && (*ep != '=') && (*np != '\0')) { ep++; np++; } if((*np == '\0') && ((*ep == '\0') || (*ep == '='))) { while(*ep++); while(ep <= (char *)NVRAM_LAST_ENV) { *sp++ = *ep++; } cksum((void *)NVRAM_FIRST_ENV, NVRAM_SIZE_ENV, 1); return(1); } else if(*ep != '\0') { while(*ep++ != '\0'); } } return(0);}inttgt_setenv(char *name, char *value){ char *ep; int envlen; /* Calculate total env mem size requiered */ envlen = strlen(name); if(envlen == 0) { return(0); } if(value != NULL) { envlen += strlen(value); } envlen += 2; /* '=' + null byte */ if(envlen > 255) { return(0); /* Are you crazy!? */ } /* If NVRAM is found to be uninitialized, reinit it. */ if(nvram_invalid) { *(char *)(NVRAM_FIRST_ENV + 2) = '\0'; *(char *)(NVRAM_FIRST_ENV + 3) = '\0'; cksum((void *)NVRAM_FIRST_ENV, NVRAM_SIZE_ENV, 1); nvram_invalid = 0; bytecopy(NVRAM_VXWORKS_DEFAULT, (char *)NVRAM_VXWORKS, sizeof(NVRAM_VXWORKS_DEFAULT)); } if(strcmp("vxWorks", name) == 0) { bytecopy(value, (char *)NVRAM_VXWORKS, envlen); return(1); } /* Remove any current setting */ tgt_unsetenv(name); /* Find end of evironment strings */ ep = (char *)NVRAM_FIRST_ENV + 2; if(*ep != '\0') { do { while(*ep++ != '\0'); } while(*ep++ != '\0'); ep--; } if((NVRAM_LAST_ENV - (int)ep) < (envlen + 1)) { return(0); /* Bummer! */ } /* * Special case heaptop must always be first since it * can change how memory allocation works. */ if(strcmp("heaptop", name) == 0) { bytecopy((char *)NVRAM_FIRST_ENV + 2, (char *)NVRAM_FIRST_ENV + 2 + envlen, (int)ep - (NVRAM_FIRST_ENV + 1)); ep = (char *)NVRAM_FIRST_ENV + 2; while(*name != '\0') { *ep++ = *name++; } if(value != NULL) { *ep++ = '='; while((*ep++ = *value++) != '\0'); } else { *ep++ = '\0'; } } else { while(*name != '\0') { *ep++ = *name++; } if(value != NULL) { *ep++ = '='; while((*ep++ = *value++) != '\0'); } else { *ep++ = '\0'; } *ep++ = '\0'; /* End of env strings */ } cksum((void *)NVRAM_FIRST_ENV, NVRAM_SIZE_ENV, 1); return(1);}/* * Calculate checksum. If 'set' checksum is calculated and set. */static intcksum(void *p, size_t s, int set){ u_int16_t sum = 0; u_int8_t *sp = p; int sz = s / 2; if(set) { *sp = 0; /* Clear checksum */ *(sp+1) = 0; /* Clear checksum */ } while(sz--) { sum += (*sp++) << 8; sum += *sp++; } if(set) { sum = -sum; *(u_int8_t *)p = sum >> 8; *((u_int8_t *)p+1) = sum; } return(sum);}/* * Simple display function to display a 4 char string or code. * Called during startup to display progress on any feasible * display before any serial port have been initialized. */voidtgt_display(char *msg, int x){ /* Have simple serial port driver */ tgt_putchar(msg[0]); tgt_putchar(msg[1]); tgt_putchar(msg[2]); tgt_putchar(msg[3]); tgt_putchar('\r'); tgt_putchar('\n');}voidtgt_devconfig(){ _pci_devinit(1); /* PCI device initialization */ config_init(); configure();}voidtgt_devinit(){ _pci_businit(1); /* PCI bus initialization */}voidtgt_machreset(){ tgt_netreset();}voidtgt_reboot(){ outb(K2_WD_ENABLE, 0x81); while(1);}voidclrhndlrs(){}inttgt_getmachtype(){ return(md_cputype());}/* * Create stubs if network is not compiled in */#ifdef INETvoidtgt_netpoll(){ splx(splhigh());}#elseextern void longjmp(label_t *, int);void gsignal(label_t *jb, int sig);voidgsignal(label_t *jb, int sig){ if(jb != NULL) { longjmp(jb, 1); }}int netopen(const char *a, int b){ return -1;}int netread(int a, void *b, int c){ return -1;}int netwrite(int a, const void *b, int c){ return -1;}int netclose(int a){ return -1;}long netlseek(int a, long b, int c){ return -1;}int netioctl(int a, int b, void *c){ return -1;}void netpoll(void){}voidtgt_netpoll(){}#if 0unsigned long__time(){ return(tgt_gettime());}#endif#endif /*INET*/
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