start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: start.S,v 1.9 2003/06/10 14:43:53 pefo Exp $ */

/*
 * Copyright (c) 2000-2002 Opsycon AB  (www.opsycon.se)
 * Copyright (c) 2000 Rtmx, Inc   (www.rtmx.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for Rtmx, Inc by
 *	Opsycon Open System Consulting AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

/*
 *  This code is partially based on the K2 init code from SBS Tech.
 */
#ifndef _LOCORE
#define _LOCORE
#endif

#include "target/pmon_target.h"

#include <pmon/dev/ns16550.h>
#include <machine/mpc_regs.h>
#include <machine/psl.h>
#include <machine/cpu.h>

#ifndef INT_MASK
#define INT_MASK(src, des)      rlwinm  des, src, 0, 17, 15
#endif  /* INT_MASK */

#define	HID0	1008
#define	HID1	1009
#define	L2CR	1017
#define	CTR	9
#define	PVR	287

#define HIADJ(x)	(x)@ha
#define HI(x)		(x)@h
#define LO(x)		(x)@l

/*
 *  Use this macro to prevent reordering by as/ld and processor
 */
#define	IORDER		eieio; sync

/*
 *  Macro used to setup CPC710.
 */

#define	CFG_WR(reg, data)			\
	lis 3, HI(reg) ; ori 3, 3, LO(reg) ;	\
	lis 4, HI(data) ; ori 4, 4, LO(data);	\
	stw 4, 0(3) ; IORDER
	
#define	CFG_RD(reg)				\
	lis 3, HI(reg) ; ori 3, 3, LO(reg) ;	\
	lwz 4, 0(3) ; IORDER
	

/*
 *  Macros used to setup BAT regs.
 */
#define IBAT_SETUP(batno, batuval, batlval)	\
	lis 3, HIADJ(batuval); addi 3, 3, LO(batuval);	\
	lis 4, HIADJ(batlval); addi 4, 4, LO(batlval);	\
	mtibatu batno, 3; mtibatl batno, 4

#define DBAT_SETUP(batno, batuval, batlval)	\
	lis 3, HIADJ(batuval); addi 3, 3, LO(batuval);	\
	lis 4, HIADJ(batlval); addi 4, 4, LO(batlval);	\
	mtdbatu batno, 3; mtdbatl batno, 4

	.space	0x100

	.globl	_start
	.globl	start
_start:
start:
	isync

        .globl  pmon_stack
stack = start - 0x4000          /* 16K PMON stack */
pmon_stack = start              /* Top of stack */
        .globl  pmon_intstack
intstack = stack - 0x2000       /* 8k PMON interrupt stack */
pmon_intstack = stack           /* Top of stack */ 

/* Clear MSR to diable interrupts and checks */

	andi.	1, 1, 0x0
	mtmsr	1		/* Clear MSR */

/* Clear mapping registers */

	li	1, 0x0
	mtibatu	0, 1
	mtibatu	1, 1
	mtibatu	2, 1
	mtibatu	3, 1
	mtdbatu	0, 1
	mtdbatu	1, 1
	mtdbatu	2, 1
	mtdbatu	3, 1
	isync
	sync
	sync
	lis	1, 0x8000
	isync
	mtsr	0, 1
	mtsr	1, 1
	mtsr	2, 1
	mtsr	3, 1
	mtsr	4, 1
	mtsr	5, 1
	mtsr	6, 1
	mtsr	7, 1
	mtsr	8, 1
	mtsr	9, 1
	mtsr	10, 1
	mtsr	11, 1
	mtsr	12, 1
	mtsr	13, 1
	mtsr	14, 1
	mtsr	15, 1
	isync
	sync
	sync

/*
 *  Get processor type
 */
	mfspr	r14, PVR
	rlwinm	r14, r14, 16, 16, 31    /* Get 16 msb */

	cmpwi	r14, CPU_TYPE_750
	beq	init_750
	cmpwi	r14, CPU_TYPE_7400
	beq	init_750

	b	init_unknown_cpu

init_750:
	li	r3, 0
	mtspr	L2CR, r3		/* Shut down L2 cache */

        mfspr   r3, HID0
        lis     r4, 0xffff
        ori     r4, r4, 0x3fff
        and     r3, r3, r4
        sync
        isync
        mtspr   HID0, r3                /* Turn off L1 caches */
        sync
        isync

        li      r4, 0x0c00
        or      r3, r3, r4
        mtspr   HID0, r3                /* Clear L1 caches */

/* Set r16 to the load vs link offset. */
init_unknown_cpu:
	bl	1f
1:
	mflr	3
	lis	16, 0xffff
	and.	16, 16, 3
	lis	4, HI(start)
	sub	16, 16, 4		/* R16 is now load offset */

/*
 *  Find out if executing in ROM or RAM. Note memory size wired to 128Mb.
 */
	lis	15, 0x0800		/* Memory size accumulator = 64MB */
	lis	4, 0xf000		/* Last 256Mb segment */
	and.	4, 4, 3
	beq	in_ram			/* We are ram loaded! */


/*
 *  Init the PCI/Memory controller (CPC710)
 */

	CFG_WR(CPC710_RSTR,   0xf0000000)
	CFG_RD(CPC710_MPSR)
	CFG_WR(CPC710_SIOC,   0x00000000)
	CFG_WR(CPC710_PIDR,   0x00000000)
	CFG_WR(CPC710_UCTL,   0x00780080)
	CFG_WR(CPC710_ABCNTL, 0x70000000)
	CFG_WR(CPC710_SRST,   0x00000000)
	CFG_WR(CPC710_ERRC,   0x00000000)
	CFG_WR(CPC710_SESR,   0x00000000)
	CFG_WR(CPC710_SEAR,   0x00000000)
	CFG_WR(CPC710_PGCHP,  0x20000060)
	CFG_WR(CPC710_GPDIR,  0x00000000)
	CFG_WR(CPC710_ATAS,   0x709c2508)
	CFG_WR(CPC710_AVDG,   0x00000000)
	CFG_WR(CPC710_MESR,   0x00000000)
	CFG_WR(CPC710_MEAR,   0x00000000)
	CFG_WR(CPC710_MCER0,  0x00000000)
	CFG_WR(CPC710_MCER1,  0x00000000)
	CFG_WR(CPC710_MCER2,  0x00000000)
	CFG_WR(CPC710_MCER3,  0x00000000)
	CFG_WR(CPC710_MCER4,  0x00000000)
	CFG_WR(CPC710_MCER5,  0x00000000)
	CFG_WR(CPC710_MCER6,  0x00000000)
	CFG_WR(CPC710_MCER7,  0x00000000)
	CFG_WR(CPC710_MCCR,   0xf2b06000)

/* PCI64 and PCI32 */

	CFG_WR(CPC710_CNFR,   0x80000003)
	CFG_WR(CPC710_BAR,    PCI64_BAR_VALUE)
	CFG_WR(CPC710_PCIENB, 0x80000000)
	CFG_WR(CPC710_CNFR,   0x00000000)
	CFG_WR(CPC710_CNFR,   0x80000002)
	CFG_WR(CPC710_BAR,    PCI32_BAR_VALUE)
	CFG_WR(CPC710_PCIENB, 0x80000000)
	CFG_WR(CPC710_CNFR,   0x00000000)


/* Config PCI64 */

	lis	0, HI(CPC710_PCI64_CFGADDR)
	ori	1, 0, LO(CPC710_PCI64_CFGADDR)
	ori	2, 0, LO(CPC710_PCI64_CFGDATA)
/**/
	lis	3, 0x8000
	ori	3, 3, CPC710_PCI_REV
	stwbrx	3, 0, 1
	IORDER
	lwbrx	26, 0, 2		/* Get device revision number */
	andi. 	26, 26, 0x00ff		/* Isolate revision bits. */
/**/
	lis	3, 0x8000
	ori	3, 3, CPC710_PCI_CMD
	stwbrx	3, 0, 1
	IORDER
	lhbrx	4, 0, 2
	lis	3, 0x001f		/* XXX! */
	ori	3, 3, 0xfca0		/* Enable and reset pci status */
	and	4, 4, 3
	lis	3, 0x0000		/* XXX! */
	ori	3, 3, 0x0107
	or	4, 4, 3
	sthbrx	4, 0, 2			/* XXX Check size of store... */
	IORDER
/**/
	lis	3, 0x8000
	ori	3, 3, CPC710_PCI_STAT
	stwbrx	3, 0, 1
	IORDER
	lhbrx	4, 0, 2
	ori	4, 4, 0xff80
	sthbrx	4, 0, 2
	IORDER
/**/
	lis	3, 0x8000
	ori	3, 3, CPC710_PCI_INT
	stwbrx	3, 0, 1
	IORDER
	li	4, 0x000f
	sthbrx	4, 0, 2
	IORDER
/**/
	lis	3, 0x8000
	ori	3, 3, CPC710_PCI_BUS
	stwbrx	3, 0, 1
	IORDER
	lhbrx	4, 0, 2
	ori	4, 4, 0x0f00
	sthbrx	4, 0, 2
	IORDER

/* Config PCI32 */

	lis	0, HI(CPC710_PCI32_CFGADDR)
	ori	1, 0, LO(CPC710_PCI32_CFGADDR)
	ori	2, 0, LO(CPC710_PCI32_CFGDATA)
/**/
	lis	3, 0x8000
	ori	3, 3, CPC710_PCI_REV
	stwbrx	3, 0, 1
	IORDER
	lwbrx	27, 0, 2		/* Get device revision number */
	andi. 	27, 27, 0x00ff		/* Isolate revision bits. */
/**/
	lis	3, 0x8000
	ori	3, 3, CPC710_PCI_CMD
	stwbrx	3, 0, 1
	IORDER
	lhbrx	4, 0, 2
	lis	3, 0x0000		/* XXX! */
	ori	3, 3, 0xfca0		/* Enable and reset pci status */
	and	4, 4, 3
	lis	3, 0x0000		/* XXX! */
	ori	3, 3, 0x0107
	or	4, 4, 3
	sthbrx	4, 0, 2			/* XXX Check size of store... */
	IORDER
/**/
	lis	3, 0x8000
	ori	3, 3, CPC710_PCI_STAT
	stwbrx	3, 0, 1
	IORDER
	lhbrx	4, 0, 2
	ori	4, 4, 0xff80
	sthbrx	4, 0, 2
	IORDER
/**/
	lis	3, 0x8000
	ori	3, 3, CPC710_PCI_BUS
	stwbrx	3, 0, 1
	IORDER
	lhbrx	4, 0, 2
	ori	4, 4, 0x0f00
	sthbrx	4, 0, 2
	IORDER

/* Configure PCI64 specific Host bridge interface */
	CFG_WR(PCI64_BAR_VALUE+PCICFG_PSEA,   0x00000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_PCIDG,  0xc0000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_PIBAR,  PCI64_IO_ADRS)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_PMBAR,  PCI64_MEM_ADRS)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_PR,     0x80008000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_ACR,    0xff000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_PMSIZE, PCI64_MEMSIZE)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_IOSIZE, PCI64_IOSIZE)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_SMBAR,  CPU_PCI64_MEM_ADRS)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_SIBAR,  CPU_PCI64_IO_ADRS)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_CTLRW,  0x02000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_PSSIZE, 0x00000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_PPSIZE, 0x00000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_BARPS,  0x00000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_BARPP,  0x00000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_INT_SET,0x00000000)

	CFG_WR(PCI64_BAR_VALUE+PCICFG_BPMDLK, 0xa0000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_TPMDLK, 0xb0000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_BIODLK, 0x90000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_TIODLK, 0x94000000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_DLKCTRL, 0xe0008000)
	CFG_WR(PCI64_BAR_VALUE+PCICFG_DLKDEV, 0xffffffff)

/* Configure PCI32 specific Host bridge interface */
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PSEA,   0x00000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PCIDG,  0x40000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PIBAR,  PCI32_ISA_IO_ADRS)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PMBAR,  PCI32_ISA_MEM_ADRS)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PR,     0x80008000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_ACR,    0xfc000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PMSIZE, PCI32_MEMSIZE)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_IOSIZE, PCI32_IOSIZE)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_SMBAR,  CPU_PCI32_ISA_MEM_ADRS)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_SIBAR,  CPU_PCI32_ISA_IO_ADRS)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_CTLRW,  0x00000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PSSIZE, 0x00000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PPSIZE, 0x000000f0)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_BARPS,  0x00000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_BARPP,  0x00000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PSBAR,  0x00000080)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_PPBAR,  0x00000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_BPMDLK, 0xc0000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_TPMDLK, 0xd0000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_BIODLK, 0x80000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_TIODLK, 0x84000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_DLKCTRL, 0xe0008000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_DLKDEV, 0xffffffff)

/* Turn off PCI32 and PCI64 resets */
	CFG_WR(PCI64_BAR_VALUE+PCICFG_CRR, 0xfc000000)
	CFG_WR(PCI32_BAR_VALUE+PCICFG_CRR, 0xfc000000)

/* Setup M1543C Config space */
	lis	0, HI(CPC710_PCI32_CFGADDR)
	ori	1, 0, LO(CPC710_PCI32_CFGADDR)
	ori	2, 0, LO(CPC710_PCI32_CFGDATA)
	lis	3, 0x8000	/* PCI_ENA */

	ori	4, 3, 0x4040
	stwbrx	4, 0, 1
	IORDER
	lis	4, 0x304a
	ori	4, 4, 0x007f
	stwbrx	4, 0, 2