pmon_target.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: pmon_target.h,v 1.3 2002/11/07 15:05:32 pefo Exp $ */

/*
 * Copyright (c) 2000 Opsycon AB  (www.opsycon.se)
 * Copyright (c) 2000 Rtmx, Inc   (www.rtmx.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for Rtmx, Inc by
 *	Opsycon Open System Consulting AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef SBD_DEBUG
#define SBD_DISPLAY(text, code)		/* No display function */
#else
extern void tgt_display __P((char *, int));
#define SBD_DISPLAY(text, code)	tgt_display(text, code)
#endif

/*
 *  Default cache parameters. Code places data correctly in register.
 */
#if 1
#define	PPC_CACHE_L2RAM 0x02            /* Sync burst */
#else
#define	PPC_CACHE_L2RAM 0x03            /* Sync burst late write */
#define	PPC_CACHE_L2RAM 0x00            /* Flow-trough */
#endif
#define	PPC_CACHE_L2PE  0x01            /* Parity enable: ON  */
#define	PPC_CACHE_L2DO  0x00            /* Data only L2:  OFF */
#define	PPC_CACHE_L2WT  0x00            /* Write through: OFF */
#define	PPC_CACHE_L2CE  0x00            /* Checkstop enable (750cx) */

#define	PPC_CACHE_SPEED		(tgt_pipefreq() / 2)

/*
 *  Stack and SMP trap code support
 *
 * XXX this is OK for a dual processor system.
 * more generic approach may be needed though.
 *
 *  Low 16K mem layout:
 *
 *  0x00000000 ->               Trap vectors.
 *  0x00003000 - 0x00003fff     Reserved.
 *  0x00004000 - 0x00005fff     Reserved.
 *  0x00006000 - 0x00007fff     Interrupt stack, currently not used.
 *  0x00008000 - 0x0000bfff     CPU 1 Info and stack.
 *  0x0000c000 - 0x0000ffff     CPU 2 info and stack.
 */

#define STACKBASE       0x000008000
#define STACKSIZE       0x000004000

#define CPUINFOADDR(reg)                \
	mfsprg  reg, 0

#define CPUSTACKADDR(reg)               \
	mfsprg  reg, 0;                 \
	addi    reg, reg, STACKSIZE

/*
 *  Name of envvar that has to be set to enable expert mode.
 */
#define	EXPERT	"sbsexpert"

/*
 *  Name of envvar that has to be set to enable extend mode.
 */
#define	CMDEXT	"cmdextend"


/*
 *  Boot loader parameters.
 */

#define	TGT_BOOT_ADR	0x00400000	/* Load 4 meg up. */
#define	TGT_BOOT_SIZ	0x00004000	/* Suck in 16k */
#define	TGT_BOOT_OFF	0x00000400	/* Start reading from byte 1024 */