start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

4:
	addi	10, 9, LO(MPC107_I2C_CSR)
	lwbrx	0, 0, 10		/* Read status */
	andi.	0, 0, I2C_CSR_MIF	/* Check interrupt MSTA */
	beq	4b			/* 0 == Nothing yet */

	addi	10, 9, LO(MPC107_I2C_CCR)
	lwbrx	0, 0, 10
	andi.	0, 0, ~I2C_CCR_MSTA & 0xffff
	stwbrx	0, 0, 10
	IORDER

	addi	10, 9, LO(MPC107_I2C_CDR)
	lwbrx	3, 0, 10

	lis	0, 16
	mtctr	0
1:
	bdnz	1b			/* Delay to settle */

	blr

/*
 *  The following was lifted out of SBS BSP.
 */

#define HI_ADR(adr) ((adr>>8)&0xff)
#define LO_ADR(adr) (adr&0xff)


/*
;
;   This function initializes the superio chip to a functional 
;   state.
;
;   Upon completion, SIO resource registers are mapped as follows:
;   Resource    Enabled     Address
;   FDC         Yes         PRI     3F0-3F7
;   IDE         No
;   UART1       Yes         COM1    3F8-3FF
;   UART2       Yes         COM2    2F8-2FF
;   ||PORT      Yes         LPT1    3BC-3BE
;   KBC         Yes         060, 064
;
;
*/


sio_init1:
	mflr    13                         /* save link register */

/* Get base addr of ISA I/O space */
	lis	6, HI(PCI_ISA_SPACE_IO_BASE)
	ori	6, 6, LO(PCI_ISA_SPACE_IO_BASE)

	addi	6, 6, M1543C_SIO_CNF_PORT /* add offset to base */
	or	3, 6, 6          /* make a copy */

/* Enter configuration mode */
	addi    4, 0, 0x51
	stb     4, 0(3)           /* write config port with configuration key */
	isync
	addi    4, 0, 0x23
	stb     4, 0(3)           /* write config port with configuration key */
	isync

	bl      check_config_mode

	b       sio_dev_init1


sio_soft_reset1:
/* Soft reset of the configuration registers */
	addi    4, 0, M1543C_SIO_RESET    /* reset super i/o */
	addi    5, 0, 0x01
	bl      sio_bw

	li  0, 0x4000
	mtctr   0
wait_sio1:  
	bdnz    wait_sio1

sio_dev_init1:
/*
* FDC (LUN 0)
*/
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select FDC LUN */
	addi    5, 0, M1543C_SIO_LUN_FDC
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable FDC */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw


/*
* LPT (LUN 3)
*/
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select LPT LUN */
	addi    5, 0, M1543C_SIO_LUN_LPT
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* disable LPT */
	addi    5, 0, M1543C_SIO_LUN_DISABLE
	bl      sio_bw
	addi    4, 0, M1543C_SIO_HIAR     /* initialize LPT address 0x3bc */
	addi    5, 0, 0x03
	bl      sio_bw
	addi    4, 0, M1543C_SIO_LOAR
	addi    5, 0, 0xBC
	bl      sio_bw
	addi    4, 0, M1543C_SIO_IRQR     /* initialize LPT irq 7 */
	addi    5, 0, 0x07
	bl      sio_bw
	addi    4, 0, M1543C_SIO_DMAR     /* initialize LPT DMA channel 3 */
	addi    5, 0, 0x03
	bl      sio_bw
	addi    4, 0, M1543C_SIO_CNFR     /* initialize LPT configuration: PS2 mode */
	addi    5, 0, 0x88
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable LPT */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw


/*
* COM1 (LUN 4)
*/
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select COM1 LUN */
	addi    5, 0, M1543C_SIO_LUN_COM1
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable COM1 */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw


/* 
* COM2 (LUN 5)
*/
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select COM2 LUN */
	addi    5, 0, M1543C_SIO_LUN_COM2
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable COM2 */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw


/* 
* Exit configuration mode
*/
	addi    4, 0, 0xbb
	stb     4, 0(3)                   /* write config port with exit key */
	isync
	mtlr    13                         /* restore link register */
	blr



sio_init:
sio_init2:
	mflr    13                         /* save link register */


/* 
* Get base addr of ISA I/O space 
*/
	lis     6, HI(PCI_ISA_SPACE_IO_BASE)
	ori     6, 6,LO(PCI_ISA_SPACE_IO_BASE)

	addi    6, 6, M1543C_SIO_CNF_PORT /* add offset to base */
	or      3, 6, 6                  /* make a copy */

/* 
* Enter configuration mode
*/
	addi    4, 0, 0x51
	stb     4, 0(3)                   /* write config port with configuration key */
	isync
	addi    4, 0, 0x23
	stb     4, 0(3)                   /* write config port with configuration key */
	isync


	bl      check_config_mode


/*
* Disable all Super I/O Devices
*/

/* 
* FDC (LUN 0x0)
*/
	addi    4, 0, M1543C_SIO_LUN_FDC  /* select FDC LUN */
	bl      sio_disable
/* 
* LPT (LUN 0x3)
*/
	addi    4, 0, M1543C_SIO_LUN_LPT  /* select LPT LUN */
	bl      sio_disable
/* 
* COM1 (LUN 0x4)
*/
	addi    4, 0, M1543C_SIO_LUN_COM1 /* select COM1 LUN */
	bl      sio_disable
/* 
* COM2 (LUN 0x5)
*/
	addi    4, 0, M1543C_SIO_LUN_COM2 /* select COM2 LUN */
	bl      sio_disable
/* 
* KBC (LUN 0x7)
*/
	addi    4, 0, M1543C_SIO_LUN_KBC  /* select keyboard LUN */
	bl      sio_disable
/* 
* UART3 (LUN 0xb)
*/
	addi    4, 0, M1543C_SIO_LUN_UART3 /* select UART3 LUN */
	bl      sio_disable
/* 
* HOTKEY (LUN 0xb)
*/
	addi    4, 0, M1543C_SIO_LUN_HOTK /* select HOTKEY LUN */
	bl      sio_disable
	b       sio_dev_init2


sio_soft_reset2:
/* 
* Soft reset of the configuration registers
*/
	addi    4, 0, M1543C_SIO_RESET    /* reset super i/o */
	addi    5, 0, 0x01
	bl      sio_bw


	li  0, 0x4000
	mtctr   0
wait_sio2:
	bdnz    wait_sio2


sio_dev_init2:
/* 
* Configure the desired Super I/O Devices 
*/

/* 
* FDC (LUN 0x0)
*/
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select FDC LUN */
	addi    5, 0, M1543C_SIO_LUN_FDC
	bl      sio_bw
	addi    4, 0, M1543C_SIO_HIAR     /* initialize FDC address */
	addi    5, 0, HI_ADR(M1543C_FDC_IO_ADRS)
	bl      sio_bw
	addi    4, 0, M1543C_SIO_LOAR
	addi    5, 0, LO_ADR(M1543C_FDC_IO_ADRS)
	bl      sio_bw
	addi    4, 0, M1543C_SIO_IRQR     /* initialize FDC (irq 5) */
	addi    5, 0, M1543C_FDC_IRQ
	bl      sio_bw
	addi    4, 0, M1543C_SIO_DMAR     /* initialize FDC DMA (channel 2) */
	addi    5, 0, M1543C_FDC_DMA
	bl      sio_bw
	addi    4, 0, M1543C_SIO_CNFR     /* initialize FDC configuration: PS2 mode */
	addi    5, 0, 0x88
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable FDC */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw
/* 
* LPT (LUN 0x3)
*/
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select LPT LUN */
	addi    5, 0, M1543C_SIO_LUN_LPT
	bl      sio_bw
	addi    4, 0, M1543C_SIO_HIAR     /* initialize LPT address (0x3bc) */
	addi    5, 0, HI_ADR(M1543C_LPT_IO_ADRS)
	bl      sio_bw
	addi    4, 0, M1543C_SIO_LOAR
	addi    5, 0, LO_ADR(M1543C_LPT_IO_ADRS)
	bl      sio_bw
	addi    4, 0, M1543C_SIO_IRQR     /* initialize LPT irq (7) */
	addi    5, 0, M1543C_LPT_IRQ
	bl      sio_bw
	addi    4, 0, M1543C_SIO_DMAR     /* initialize LPT DMA channel 3 */
	addi    5, 0, M1543C_LPT_DMA
	bl      sio_bw
	addi    4, 0, M1543C_SIO_CNFR     /* initialize LPT default configuration: IRQ active low, ECP fifi treshold 0001, SPP mode*/
	addi    5, 0, 0x8C
	bl      sio_bw
	addi    4, 0, M1543C_SIO_CNF2R    /* initialize LPT default configuration: ext mode, 12MHz clock, no EPP timeout interrupt, burtst mode DMAin ECP */
	addi    5, 0, 0x85
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable LPT */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw
/* 
* COM1 (LUN 0x4)
*/
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select COM1 LUN */
	addi    5, 0, M1543C_SIO_LUN_COM1
	bl      sio_bw
	addi    4, 0, M1543C_SIO_HIAR     /* initialize COM1 address (0x3f8) */
	addi    5, 0, HI_ADR(M1543C_COM1_IO_ADRS)
	bl      sio_bw
	addi    4, 0, M1543C_SIO_LOAR
	addi    5, 0, LO_ADR(M1543C_COM1_IO_ADRS)
	bl      sio_bw
	addi    4, 0, M1543C_SIO_IRQR     /* initialize COM1 irq (4) */
	addi    5, 0, M1543C_COM1_IRQ
	bl      sio_bw
	addi    4, 0, M1543C_SIO_CNFR     /* initialize COM1 default configuration: normal clock source, high speed mode disabled, midi disabled */
	addi    5, 0, 0x00
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable COM1 */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw
/* 
* COM2 (LUN 0x5)
*/
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select COM2 LUN */
	addi    5, 0, M1543C_SIO_LUN_COM2
	bl      sio_bw
	addi    4, 0, M1543C_SIO_HIAR     /* initialize COM2 address (0x2f8) */
	addi    5, 0, HI_ADR(M1543C_COM2_IO_ADRS)
	bl      sio_bw
	addi    4, 0, M1543C_SIO_LOAR
	addi    5, 0, LO_ADR(M1543C_COM2_IO_ADRS)
	bl      sio_bw
	addi    4, 0, M1543C_SIO_IRQR     /* initialize COM1 irq (3) */
	addi    5, 0, M1543C_COM2_IRQ
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable COM2 */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw
/* 
* KBC (LUN 0x7)
*/
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select keyboard LUN */
	addi    5, 0, M1543C_SIO_LUN_KBC
	bl      sio_bw
	addi    4, 0, M1543C_SIO_IRQR     /* initialize keyboard irq (1) */
	addi    5, 0, M1543C_KBC_IRQ
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable keyboard */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw



/*
* Enable all desired Super I/O Devices
*/

/* 
* FDC (LUN 0x0)
*/
	addi    4, 0, M1543C_SIO_LUN_FDC  /* select FDC LUN */
	bl      sio_enable
/* 
* LPT (LUN 0x3)
*/
	addi    4, 0, M1543C_SIO_LUN_LPT  /* select LPT LUN */
	bl      sio_enable
/* 
* COM1 (LUN 0x4)
*/
	addi    4, 0, M1543C_SIO_LUN_COM1 /* select COM1 LUN */
	bl      sio_enable
/* 
* COM2 (LUN 0x5)
*/
	addi    4, 0, M1543C_SIO_LUN_COM2 /* select COM2 LUN */
	bl      sio_enable
/* 
* KBC (LUN 0x7)
*/
	addi    4, 0, M1543C_SIO_LUN_KBC  /* select keyboard LUN */
	bl      sio_enable



/* 
* Exit configuration mode
*/
	addi    4, 0, 0xbb
	stb     4, 0(3)                   /* write config port with exit key */
	isync
	mtlr    13                         /* restore link register */
	blr


/*
; routine: sio_enable
;   this function enables one device of the SIO chip
; call:
;   sio_enable(3=sioaddr, 4=device LUN)
; return:
;   none
*/
sio_enable:
	mflr    14                         /* save link register */
	or      5, 4, 4                  /* copy device LUN from 4 to 5 */
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select index register */
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* enable device */
	addi    5, 0, M1543C_SIO_LUN_ENABLE
	bl      sio_bw
	mtlr    14                         /* restore link register */
	blr

/*
; routine: sio_disable
;   this function disables one device of the SIO chip
; call:
;   sio_disable(3=sioaddr, 4=device LUN)
; return:
;   none
*/
sio_disable:
	mflr    14                         /* save link register */
	or      5, 4, 4                  /* copy device LUN from 4 to 5 */
	addi    4, 0, M1543C_SIO_LUN_IDX  /* select index register */
	bl      sio_bw
	addi    4, 0, M1543C_SIO_ENR      /* disable device */
	addi    5, 0, M1543C_SIO_LUN_DISABLE
	bl      sio_bw
	mtlr    14                         /* restore link register */
	blr

/*
; routine: sio_bw
;   this function writes a register to the SIO chip
; call:
;   sio_bw(sioaddr, regnum, value)
; return:
;   none
*/
sio_bw:
	stb 4,0(3)    /* write register offset to index port */
	eieio
	isync
	stb 5,1(3)    /* write value to data port */
	eieio
	isync
	blr		/* return to caller */
/*
; routine: sio_br
;   this function reads a register from the SIO chip
; call:
;   sioInit(sioaddr, regnum)
; return:
;   register value
*/
sio_br:
	stb 4,0(3)    /* write index register with register offset */
	eieio
	isync
	lbz 3,1(3)    /* retrieve specified reg offset contents */
	eieio
	isync
	bclr    20,0        /* return to caller */


check_config_mode:
	mflr    14                         /* save link register */
	mr      3, 6                      /* 6 contains config port fo super i/o */
	addi    4, 0, 0x20                /* read device identification registers 0x20 */
	bl      sio_br
	cmpli   0, 0, 3, 0x43              /* compare with ALI defined value */
	bne     error_loop

	mr      3, 6                      /* 6 contains config port fo super i/o */
	addi    4, 0, 0x21                /* read device identification registers 0x21 */
	bl      sio_br
	cmpli   0, 0, 3, 0x15              /* compare with ALI defined value */
	bne     error_loop

	mr      3, 6                      /* 6 contains config port fo super i/o */
	mtlr    14                         /* restore link register */
	blr                                 /* return to calling function */


error_loop:
	b       error_loop