start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: start.S,v 1.6 2002/11/07 15:05:31 pefo Exp $ */

/*
 * Copyright (c) 2000-2002 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#include "target/pmon_target.h"

#include "machine/pmon_arch.h"
#include "pmon/dev/mpc107reg.h"
#include "pmon/dev/m1543reg.h"
#include "pmon/dev/ns16550.h"

#ifndef INT_MASK
#define INT_MASK(src, des)      rlwinm  des, src, 0, 17, 15
#endif  /* INT_MASK */

#define	HID0	1008
#define	HID1	1009
#define	L2CR	1017
#define	CTR	9

#define HIADJ(x)	(x)@ha
#define HI(x)		(x)@h
#define LO(x)		(x)@l

/*
 *  Use this macro to prevent reordering by as/ld and processor
 */
#define	IORDER		eieio; sync

/*
 *  Macros used to access MPC107 config space.
 *  Depend on register 1, 2 and 3 set up correctly.
 */

#define	MPC_CFG_AD(reg)						\
	ori 0, 22, ((reg) & ~3) ; stwbrx 0, 0, 20 ;		\
	IORDER

#define	MPC_CFG_WR(reg, data)					\
	ori 4, 22, ((reg) & ~3) ; stwbrx 4, 0, 20 ; sync;	\
	lis 4, HI(data) ; ori 4, 4, LO(data);			\
	stwbrx 4, 0, 21 ; IORDER
	
#define	MPC_CFG_RWR(reg)					\
	ori 0, 22, ((reg) & ~3) ; stwbrx 0, 0, 20 ; sync;	\
	stwbrx 4, 0, 21 ; IORDER
	
#define	MPC_CFG_RD(reg)						\
	ori 4, 22, ((reg) & ~3) ; stwbrx 4, 0, 20 ; sync;	\
	lwbrx 4, 0, 21 ; IORDER
	
#define	MPC_CFG_RD3(reg)					\
	ori 4, 22, ((reg) & ~3) ; stwbrx 4, 0, 20 ; sync;	\
	lwbrx 3, 0, 21 ; IORDER
	
/*
 *  Macros used to setup BAT regs.
 */
#define IBAT_SETUP(batno, batuval, batlval)	\
	lis 3, HIADJ(batuval); addi 3, 3, LO(batuval);	\
	lis 4, HIADJ(batlval); addi 4, 4, LO(batlval);	\
	mtibatu batno, 3; mtibatl batno, 4

#define DBAT_SETUP(batno, batuval, batlval)	\
	lis 3, HIADJ(batuval); addi 3, 3, LO(batuval);	\
	lis 4, HIADJ(batlval); addi 4, 4, LO(batlval);	\
	mtdbatu batno, 3; mtdbatl batno, 4


	.space	0x100

	.globl	_start
	.globl	start
_start:
start:

	.globl	pmon_stack
stack = start - 0x4000		/* 16K PMON stack */
pmon_stack = start		/* Top of stack */
	.globl	pmon_intstack
intstack = stack - 0x2000	/* 8k PMON interrupt stack */
pmon_intstack = stack		/* Top of stack */

/* Clear MSR to diable interrupts and checks */

	andi.	1, 1, 0x0
	mtmsr	1		/* Clear MSR */

/* Unlock special registers and turn off card fail LED */
	lis	3, HIADJ(VG4_LOCKR)
	li	4, VG4_LOCKR_UNLOCK
	stb	4, LO(VG4_LOCKR)(3)
	li	4, 0
	stb	4, LO(VG4_LEDCR)(3)
	li	4, VG4_WCR_DIS
	stb	4, LO(VG4_WCR)(3)

/* Clear BAT and Segment mapping registers */

	li	1, 0x0
	mtibatu	0, 1
	mtibatu	1, 1
	mtibatu	2, 1
	mtibatu	3, 1
	mtdbatu	0, 1
	mtdbatu	1, 1
	mtdbatu	2, 1
	mtdbatu	3, 1
	isync
	sync
	sync
	lis	1, 0x8000
	isync
	mtsr	0, 1
	mtsr	1, 1
	mtsr	2, 1
	mtsr	3, 1
	mtsr	4, 1
	mtsr	5, 1
	mtsr	6, 1
	mtsr	7, 1
	mtsr	8, 1
	mtsr	9, 1
	mtsr	10, 1
	mtsr	11, 1
	mtsr	12, 1
	mtsr	13, 1
	mtsr	14, 1
	mtsr	15, 1
	isync
	sync
	sync

/* Turn off caches and invalidate them */

#if 0  /* Reset should turn it off... */
	mfspr	3, L2CR
	andis.	3, 3, 0x7fff
	mtspr	L2CR, 3
	isync
#endif
/**/
	mfspr   3, HID0
	isync
	rlwinm  4, 3, 0, 18, 15	/* clear d15 and d16 */
	sync
	isync
	mtspr   HID0, 4 	/* turn off caches */
	isync


	lis	3, 0		/* XXX 603/740 specific code */
	ori	3, 3, 0x0c00	/* Enable & invalidate bits */
	or	4, 4, 3
	sync
	isync
	mtspr	HID0, 4
	andc	4, 4, 3
	isync

	li	11, 0x2000	/* No harm */
	mtspr	CTR, 11
1:
	bdnz	1b

	isync
	mtspr	HID0, 4
	isync

#if 0
	ori	4, 4, 0x8800
	isync
	mtspr	HID0, 4			/* turn on i-cache for speed */
	rlwinm	4, 4, 0, 21, 19		/* clear the ICFI bit */
	isync
	mtspr	HID0, 4
#endif

/* Get CPU type */
	mfspr	28, 287
	rlwinm	28, 28, 16, 16, 31

/* Set r16 to the load vs link offset. */
	bl	1f
1:
	mflr	3
	lis	16, 0xffff
	and.	16, 16, 3
	lis	4, HI(start)
	sub	16, 16, 4		/* R16 is now load offset */

/*
 *  Find out if executing in ROM or RAM. Note memory size wired to 64Mb.
 */
	lis	15, 0x0400		/* Memory size accumulator = 64MB */
	lis	4, 0xf000		/* Last segment */
	and.	4, 4, 3
	beq	in_ram			/* We are ram loaded! */


/*
 * This is a cold boot startup. Do HW initialisation
 */

/* Fixed regs 20 = PCI CONFIG ADDR, 21 = PCI_CONFIG_DATA, 22 = CONF DEV */
	lis	20, HI(MPC107_CONF_ADDR)
	ori	21, 20, LO(MPC107_CONF_DATA)
	ori	20, 20, LO(MPC107_CONF_ADDR)
	lis	22, 0x8000		/* config space access enable */

	MPC_CFG_WR(MPC107_CFG_EUMBBAR, MPC107_EUMBAR)
	MPC_CFG_WR(MPC107_CFG_PCSRBAR, MPC107_EUMBAR)

/* Turn off MEMGO to disable memory controller */
	MPC_CFG_RD(MPC107_CFG_MCFG1)
	lis	0, 0x0008
	andc	4, 4, 0
	MPC_CFG_RWR(MPC107_CFG_MCFG1)

/* Set up the cache controller */
	MPC_CFG_RD(MPC107_CFG_PICR1)
	lis	0, 0xff38
	ori	0, 0, 0x0300
	and	4, 4, 0
	lis	0, 0x0005		/* CPU type = 603/7x0 and MAP A! */
	ori	0, 0, 0x1a90		/* Default = NO L2 cache */
#if 0
	ori	0, 0, 0x0004		/* PCI prefetch */
#endif
	or	4, 4, 0
	MPC_CFG_RWR(MPC107_CFG_PICR1)

/* Set PCI command to default values and clear any error status. */
	MPC_CFG_RD(MPC107_PCI_CMD)
	lis	0, 0xffff
	ori	0, 0, 0xfca0
	and	4, 4, 0			/* Preserve bits */
	ori	4, 4, 0x0106		/* SERR, MASTER, MEMORY ENABLE */
	MPC_CFG_RWR(MPC107_PCI_CMD)

/* Set up the memory controller */
	MPC_CFG_AD(MPC107_CFG_ERR_EN1)
	lbz	4, 0(21)
	andi.	4, 4, 0xfb		/* Disable error reporting */
	stb	4, 0(21)
	IORDER

	MPC_CFG_AD(MPC107_CFG_ERR_EN2)
	lbz	4, 0(21)
	andi.	4, 4, 0xf7		/* Disable error reporting */
	stb	4, 0(21)
	IORDER

/* Adjust wait states for ROM access */
	MPC_CFG_RD(MPC107_CFG_MCFG1)
	lis	0, 0x0780		/* 100Mhz */
	ori	0, 0, 0x0000		/* SDRAM 12 row bits */
	and	4, 4, 0			/* Preserve reserved bits */
	or	4, 4, 0
	MPC_CFG_RWR(MPC107_CFG_MCFG1)
/**/
	lis	4, 0xa00c		/* 100Mhz, inline read + writes */
	ori	4, 4, 0x0f31		/* 100Mhz, RMW parity */
	MPC_CFG_RWR(MPC107_CFG_MCFG2)
/**/
	MPC_CFG_RD(MPC107_CFG_MCFG3)
	lis	0, 0x000f
	ori	0, 0, 0xffff
	and	4, 4, 0			/* Preserve bits */
	oris	4, 4, 0x7740		/* BSTOPRE_M 7, REFREC 7 clk, RDLAT 4 */
	MPC_CFG_RWR(MPC107_CFG_MCFG3)
/**/
	MPC_CFG_RD(MPC107_CFG_MCFG4)
	lis	0, 0x0083
	and	4, 4, 0
	oris	4, 4, 0x2562
	ori	4, 4, 0x2239
	MPC_CFG_RWR(MPC107_CFG_MCFG4)
/**/
	MPC_CFG_AD(MPC107_CFG_MBEN)	/* Bank enables */
	li	4, 0x0
	stb	4, (MPC107_CFG_MBEN & 3)(21)	/* Disables all banks */
/**/
/* Preleminary setup Bank 64 */
	MPC_CFG_WR(MPC107_CFG_MSTA_03, 0xc0804000)
	MPC_CFG_WR(MPC107_CFG_MSTA_47, 0xc0804000)
	MPC_CFG_WR(MPC107_CFG_EMSTA_03, 0x00000000)
	MPC_CFG_WR(MPC107_CFG_EMSTA_47, 0x01010101)
	MPC_CFG_WR(MPC107_CFG_MEND_03, 0xffbf7f3f)
	MPC_CFG_WR(MPC107_CFG_MEND_47, 0xffbf7f3f)
	MPC_CFG_WR(MPC107_CFG_EMEND_03, 0x00000000)
	MPC_CFG_WR(MPC107_CFG_EMEND_47, 0x01010101)
	lis	15, 0x0400		/* Memory size accumulator  = 64MB */
	li	4, 1
	MPC_CFG_AD(MPC107_CFG_MBEN)	/* Bank enables */
	stb	4, (MPC107_CFG_MBEN & 3)(21)
/**/
	MPC_CFG_AD(MPC107_CFG_MPMR)
	li	4, 0x8a			/* 100Mhz */
	stb	4, (MPC107_CFG_MPMR & 3)(21)
/**/
	MPC_CFG_AD(MPC107_CFG_ODCR)
	li	4, (PCI50OHM|CPU40OHM|MEM13OHM|PCICLK13OHM|MEMCLK13OHM)
	stb	4, (MPC107_CFG_ODCR & 3)(21)
/**/
	MPC_CFG_AD(MPC107_CFG_CDCR)
	li	4, 0x0203
	sthbrx	4, 0, 21
/**/
	MPC_CFG_AD(MPC107_CFG_MDCR)
	li	4, 0
	stb	4, (MPC107_CFG_MDCR & 3)(21)
/**/
	li	4, 10000
	mtctr	4
1:
	bdnz	1b		/* Delay to allow memory to initialize */
/**/
	MPC_CFG_RD(MPC107_CFG_MCFG1)
	oris	4, 4, 0x0008
	MPC_CFG_RWR(MPC107_CFG_MCFG1)
/**/
	li	4, 10000
	mtctr	4
1:
	bdnz	1b		/* Delay to allow memory to initialize */
/**/

/*
 *  Initialise the M1543C basics
 */
	lis	22, 0x8000
	ori	22, 22, (18 << 11) /* New config base address */
/**/
	MPC_CFG_AD(M1543C_PCSAD)
	li	4, 0x03
	stb	4, 1(21)
	li	4, 0x01
	stb	4, 2(21)
	li	4, 0x00
	stb	4, 3(21)
/**/
	MPC_CFG_AD(M1543C_GPIS)
	lbz	4, (M1543C_GPIS & 3)(21)
	andi.	4, 4, 0xfb
	stb	4, (M1543C_GPIS & 3)(21)
/**/
	MPC_CFG_AD(M1543C_PMU_SMIRB)
	lbz	4, (M1543C_PMU_SMIRB & 3)(21)
	ori	4, 4, 0x06
	stb	4, (M1543C_PMU_SMIRB & 3)(21)
/**/
	MPC_CFG_AD(M1543C_BCSC)
	lbz	4, (M1543C_BCSC & 3)(21)
	ori	4, 4, 0x40		/* Enable flash mem write */
	stb	4, (M1543C_BCSC & 3)(21)
/**/
	MPC_CFG_AD(M1543C_PMU_ODGPOII)
	lbz	4, (M1543C_PMU_ODGPOII & 3)(21)
	andi.	4, 4, 0xf9		/* Enable flash and SPD prot */
	stb	4, (M1543C_PMU_ODGPOII & 3)(21)
/**/
	MPC_CFG_AD(M1543C_ISAC1)
	lbz	4, (M1543C_ISAC1 & 3)(21)
	andi.	4, 4, 0x07
	ori	4, 4, 0x01		/* ISA clock = PCICLK / 2 */
	stb	4, (M1543C_ISAC1 & 3)(21)

/*
 *  Here we need to enable the IBAT/DBAT (after setup) to be able to
 *  access 0xfff00000+ if processor is 740/750!
 */
        IBAT_SETUP(0, 0x00001fff, 0x0000001a)	/* Ram segment */
        IBAT_SETUP(1, 0xf0001fff, 0xf000002a)	/* Boot rom segment */
        IBAT_SETUP(2, 0x00000000, 0x00000000)	/* Disable */
        IBAT_SETUP(3, 0x00000000, 0x00000000)	/* Disable */
        DBAT_SETUP(0, 0x00001fff, 0x0000001a)	/* Ram segment */
        DBAT_SETUP(1, 0xc0001fff, 0xc000002a)	/* PCI mem */
        DBAT_SETUP(2, 0x80001fff, 0x8000002a)	/* PCI I/O */
        DBAT_SETUP(3, 0xf0001fff, 0xf000002a)	/* Boot rom segment */

	mfmsr	4
	ori	4, 4, 0x0010	/* Translation enable */
	isync
	mtmsr	4
	sync

/*
 * Init super I/O chip
 */
	bl	sio_init

/*
 *  Determine and set up final memory configuration.
 */

spd_init:
	bl	i2c_init
	li	3, 31
	bl	i2c_read
	ori	12, 3, 0		/* Bank density */
	li	3, 5
	bl	i2c_read
	srwi	3, 3, 1			/* Number of banks */
	slw	12, 12, 3		/* Multiply by number of banks */
	li	3, 3
	bl	i2c_read		/* Get number of row address bits */
	ori	13, 3, 0

	lis	20, HI(MPC107_CONF_ADDR)
	ori	21, 20, LO(MPC107_CONF_DATA)
	ori	20, 20, LO(MPC107_CONF_ADDR)
	lis	22, 0x8000		/* config space access enable */

/* Turn off MEMGO to disable memory controller */
	MPC_CFG_RD(MPC107_CFG_MCFG1)
	lis	0, 0x0008
	andc	4, 4, 0
	MPC_CFG_RWR(MPC107_CFG_MCFG1)

/* Adjust wait states for ROM access */
	MPC_CFG_RD(MPC107_CFG_MCFG1)
	lis	0, 0x0780		/* 100Mhz */
	ori	0, 0, 0x0000		/* SDRAM 12 row bits */
	and	4, 4, 0			/* Preserve reserved bits */

	cmpwi	13, 13			/* Check if 13 row bits */
	bne	1f
	ori	0, 0, 0x0002		/* Change SDRAM to 13 row bits */
1:
	or	4, 4, 0
	MPC_CFG_RWR(MPC107_CFG_MCFG1)
/**/
	lis	4, 0xa00c		/* 100Mhz, inline read + writes */
	ori	4, 4, 0x0f31		/* 100Mhz, RMW parity */
	MPC_CFG_RWR(MPC107_CFG_MCFG2)
/**/
	MPC_CFG_RD(MPC107_CFG_MCFG3)
	lis	0, 0x000f
	ori	0, 0, 0xffff
	and	4, 4, 0			/* Preserve bits */
	oris	4, 4, 0x7740		/* BSTOPRE_M 7, REFREC 7 clk, RDLAT 4 */
	MPC_CFG_RWR(MPC107_CFG_MCFG3)
/**/
	MPC_CFG_RD(MPC107_CFG_MCFG4)
	lis	0, 0x0083
	and	4, 4, 0
	oris	4, 4, 0x2562
	ori	4, 4, 0x2239
	MPC_CFG_RWR(MPC107_CFG_MCFG4)
/**/
	MPC_CFG_AD(MPC107_CFG_MBEN)	/* Bank enables */
	li	4, 0x0
	stb	4, (MPC107_CFG_MBEN & 3)(21)	/* Disables all banks */
/**/
	cmpwi	12, 0x10
	bne	check_if_128
/* Bank 64 */
fallback_to_64: