cpci680.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: cpci680.h,v 1.1 2002/05/08 19:23:02 patrik Exp $ */

/*
 * Copyright (c) 2002 Patrik Lindergren   (www.lindergren.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Patrik Lindergren
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef __CPCI680_H__
#define __CPCI680_H__

#define PCI_ISA_IO_SPACE	MPC107_PCI_ISA_IO_BASE
#define PCI_MEM_BASE		MPC107_PCI_MEM_BASE

/*
 *  I/O ports.
 */

#define	CLOCK_ADDR		(MPC107_PCI_ISA_IO_BASE + 0x070)
#define	CLOCK_DATA		(MPC107_PCI_ISA_IO_BASE + 0x071)

#define BOOTFLASH1_BASE		0xfff00000
#define BOOTFLASH1_END		0xfff80000
#define BOOTFLASH1_SIZE		(BOOTFLASH1_END - BOOTFLASH1_BASE)
#define BOOTFLASH2_BASE		0xfff80000
#define BOOTFLASH2_END		0xffffffff
#define BOOTFLASH2_SIZE		(BOOTFLASH2_END - BOOTFLASH2_BASE)
#define USERFLASH_BASE		0xff000000
#define USERFLASH_END		0xff7fffff
#define USERFLASH_SIZE		(USERFLASH_END - USERFLASH_BASE)
#define BOOTFLASH_END		0xff7fffff
#define BOOTFLASH_SIZE		(USERFLASH_END - USERFLASH_BASE)

#define COM1_BASE_ADDR		(MPC107_PCI_ISA_IO_BASE + 0x3f8)
#define COM2_BASE_ADDR		(MPC107_PCI_ISA_IO_BASE + 0x2f8)

#define COM1_FREQ		1843200
#define COM2_FREQ		1843200

#define CPCI680_DCCR_A		(MPC107_PCI_ISA_IO_BASE + 0x308)
#define CPCI680_CS_SIGNAL	(MPC107_PCI_ISA_IO_BASE + 0x310)
#define CPCI680_DCCR_B		(MPC107_PCI_ISA_IO_BASE + 0x348)		

#define	DCCR_A_L2SIZE_SHIFT	6
#define	DCCR_A_L2SIZE_MASK	0xC0
#define	DCCR_A_L2SIZE(cr) \
			    (((cr) >> DCCR_A_L2SIZE_SHIFT) & DCCR_A_L2SIZE_MASK)

#define	DCCR_A_GPSW_SHIFT	5
#define	DCCR_A_GPSW_MASK	0x20
#define	DCCR_A_GPSW(cr) \
			  (((cr) >> DCCR_A_GPSW_SHIFT) & DCCR_A_GPSW_MASK)

#define	DCCR_A_BOOTXCHGSW_SHIFT	4
#define	DCCR_A_BOOTXCHGSW_MASK	0x10
#define	DCCR_A_BOOTXCHGSW(cr) \
			(((cr) >> DCCR_A_BOOTXCHGSW_SHIFT) & DCCR_A_BOOTXCHGSW_MASK)

#define	DCCR_A_ONBOARD_MEM_SHIFT	0
#define	DCCR_A_ONBOARD_MEM_MASK		0x0f
#define	DCCR_A_ONBOARD_MEM(cr) \
			      (((cr) >> DCCR_A_ONBOARD_MEM_SHIFT) & DCCR_A_ONBOARD_MEM_MASK)

#define	DCCR_B_FAST_BUSFREQ_SHIFT	6
#define	DCCR_B_FAST_BUSFREQ_MASK	0xC0
#define	DCCR_B_FAST_BUSFREQ(cr) \
			       (((cr) >> DCCR_B_FAST_BUSFREQ_SHIFT) & DCCR_B_FAST_BUSFREQ_MASK)

#define	DCCR_B_SLOW_BUSFREQ_SHIFT	4
#define	DCCR_B_SLOW_BUSFREQ_MASK	0x30
#define	DCCR_B_SLOW_BUSFREQ(cr) \
				(((cr) >> DCCR_B_SLOW_BUSFREQ_SHIFT) & DCCR_B_SLOW_BUSFREQ_MASK)

#define	DCCR_B_FASTBUS_SHIFT	3
#define	DCCR_B_FASTBUS_MASK	0x08
#define	DCCR_B_FASTBUS(cr) \
				(((cr) >> DCCR_B_FASTBUS_SHIFT) & DCCR_B_FASTBUS_MASK)

#define	DCCR_B_REGMODE_SHIFT	2
#define	DCCR_B_REGMODE_MASK	0x04
#define	DCCR_B_REGMODE(cr) \
			   (((cr) >> DCCR_B_REGMODE_SHIFT) & DCCR_B_REGMODE_MASK)

#define	DCCR_B_MODULE_CODE_SHIFT	0
#define	DCCR_B_MODULE_CODE_MASK		0x03
#define	DCCR_B_MODULE_CODE(cr) \
			   (((cr) >> DCCR_B_MODULE_CODE_SHIFT) & DCCR_B_MODULE_CODE_MASK)


/*
 *  NV-Ram.
 */
#define NVRAM_BASE		(USERFLASH_BASE + 0xF0000)
#define NVRAM_SIZE		0x7F00	/* How many bytes */
#define NVRAM_OFFS		0x0000
#define NVRAM_MAXSIZE		0xffff

#ifdef VXWORKS
#define	NVRAM_VXWORKS		(NVRAM_BASE + 0x7f00)
#define	NVRAM_VXWORKS_DEFAULT \
"dc(0,0)host:/usr/vw/config/cpci680/vxWorks h=90.0.0.3 e=90.0.0.50 u=target"
#endif /* VXWORKS */

#endif /* __CPCI680_H__ */