start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	addis   0,0,0xFC00
	or	0,6,0

//do configuration read to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bits 27..24 at offset 0xFC
	or	9,8,8	// move (8)->(9)
	andis.	9,9,0xFFFF
	andi.	8,8,0xFFF0	// clear bits 27..24
	or	8,9,8
	
//load DRAM port code from address 0xFE000348, mask 0x30 for speed
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)

// FASTBUS, bit 3, 0 = SLOW_BUSFREQ (mask 0x30)
//                 1 = FAST_BUSFREQ (mask 0xC0)
// 66MHz = 0x30; DRAM port values for SLOW_BUSFREQ bus clock
// 83MHz = 0x20  (mask = 0x30)
// 99MHz = 0x10
// res.  = 0x00
// 66MHz = 0xC0; DRAM port values for FAST_BUSFREQ bus clock
// 83MHz = 0x80  (mask = 0xC0)
// 99MHz = 0x40
// res.  = 0x00
        andi.   11,11,0x0008        // mask FASTBUS bit3
        
        cmpwi   cr2,11,0x0008        // Do we have FASTBUS=1?
        beq     cr2,Actopre99FAST     // Yes, FASTBUS=1 branch to FAST_BUSFREQ    



// SLOW_BUSFREQ

Actopre99SLOW:
				      // No, FASTBUS=0=SLOW_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x0030        // mask bits SLOW_BUSFREQ

				      // Check for 66MHz
        cmpwi   cr2,11,0x0030        // Do we have 66MHz?
        beq     cr2,Actopre66SLOW     // Yes, jmp if we have 66MHz
        cmpwi   cr2,11,0x0020        // Do we have 83MHz?
        beq     cr2,Actopre83SLOW     // Yes, jmp if we have 83MHz
				      // Must be 99MHz...
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// Actopre = 6; 99MHz
	ori	8,8,0x0006    //ACTOPRE = 6; 99MHz
	b       ActopreEndALL

Actopre83SLOW:
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// PRETOACT = 5; 83MHz
	ori	8,8,0x0005    //ACTOPRE = 5; 83MHz
	b       ActopreEndALL
	
Actopre66SLOW:
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// PRETOACT = 4; 66MHz
	ori	8,8,0x0004    //ACTOPRE = 4; 66MHz
	b       ActopreEndALL
	
	
	
// FAST_BUSFREQ	
	
Actopre99FAST:
				      // No, FASTBUS=1=FAST_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x00C0        // mask bits FAST_BUSFREQ

				      // Check for 66MHz
        cmpwi   cr2,11,0x00C0        // Do we have 66MHz?
        beq     cr2,Actopre66SLOW     // Yes, jmp if we have 66MHz
        cmpwi   cr2,11,0x0080        // Do we have 83MHz?
        beq     cr2,Actopre83SLOW     // Yes, jmp if we have 83MHz
				      // Must be 99MHz...
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// Actopre = 6; 99MHz
	ori	8,8,0x0006    //ACTOPRE = 6; 99MHz
	b       ActopreEndALL

Actopre83FAST:
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// PRETOACT = 5; 83MHz
	ori	8,8,0x0005    //ACTOPRE = 5; 83MHz
	b       ActopreEndALL
	
Actopre66FAST:
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// PRETOACT = 4; 66MHz
	ori	8,8,0x0004    //ACTOPRE = 4; 66MHz
		

ActopreEndALL:
//do configuration write to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


//#//#######################################################
// setup ACTORW=2-3, Activate to read/write interval
// tRCD=30ns, 30ns*66MHz=1.98 ->2
// tRCD=30ns, 30ns*83MHz=2.49 ->3
// tRCD=30ns, 30ns*99MHz=2.97 ->3
// 2 = minimum for registered mode
// 3 = minimum for inline buffer mode
//#########################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

// ACTORW, set bits 7..4 = 0010b = 2, offset 0xFC,
	addis   0,0,0xFC00
	or	0,6,0

//do configuration read to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bits 7..4 at offset 0xFC
	or	9,8,8	// move (8)->(9)
	andis.	9,9,0x0FFF
	andi.	8,8,0xFFFF	// clear bits 7..4
	or	8,9,8
	
//load DRAM port code from address 0xFE000348
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)

// FASTBUS, bit 3, 0 = SLOW_BUSFREQ (mask 0x30)
//                 1 = FAST_BUSFREQ (mask 0xC0)
// 66MHz = 0x30; DRAM port values for SLOW_BUSFREQ bus clock
// 83MHz = 0x20  (mask = 0x30)
// 99MHz = 0x10
// res.  = 0x00
// 66MHz = 0xC0; DRAM port values for FAST_BUSFREQ bus clock
// 83MHz = 0x80  (mask = 0xC0)
// 99MHz = 0x40
// res.  = 0x00
        andi.   11,11,0x0008        // mask FASTBUS bit3
        
        cmpwi   cr2,11,0x0008        // Do we have FASTBUS=1?
        beq     cr2,Actorw66FAST      // Yes, FASTBUS=1 branch to FAST_BUSFREQ    



//SLOW_BUSFREQU

Actorw66SLOW:
				      // No, FASTBUS=0=SLOW_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x0030        // mask bits SLOW_BUSFREQ
        
				      // Check for 66MHz
        cmpwi   cr2,11,0x0030        // Do we have 66MHz?
        bne     cr2,Actorw8399SLOW    // No, jmp if we have 83/99MHz

// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// ACTORW = 3; 66MHz
	oris	8,8,0x3000          //ACTORW = 3; 66MHz
	b       ActorwEndALL

Actorw8399SLOW:
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// ACTORW = 3; 83/99MHz
	oris	8,8,0x3000          //ACTORW = 3; 83/99MHz
	b       ActorwEndALL



//FAST_BUSFREQ	
	
Actorw66FAST:

				      // No, FASTBUS=1=FAST_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x00C0        // mask bits FAST_BUSFREQ
        
				      // Check for 66MHz
        cmpwi   cr2,11,0x00C0        // Do we have 66MHz?
        bne     cr2,Actorw8399FAST    // No, jmp if we have 83/99MHz

// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// ACTORW = 3; 66MHz, on FAST_BUSFREQ we have onboard in-line mode ECC
// actorw minimum for that is 3.
	oris	8,8,0x3000          //ACTORW = 3; 66MHz
	b       ActorwEndALL

Actorw8399FAST:
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// ACTORW = 3; 83/99MHz
	oris	8,8,0x3000          //ACTORW = 3; 83/99MHz

	
	
ActorwEndALL:
//do configuration write to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


//#########################################################
// setup self refresh enable SREN during Sleep/suspend mode
//########################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

// SREN, set bit 18 = 1, offset 0xF0,
	addis   0,0,0xF000
	or	0,6,0

//do configuration read to offset F0h;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 18 at offset 0xF0
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFFFF
	andi.	8,8,0xFBFF	// clear bit 18
	or	8,9,8
	
	ori	8,8,0x0400    //SREN = on

//do configuration write to offset F0h;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


//#########################################################
// setup DIMM mode REGDIMM, MCCR4, 0xFC, bit15
//#########################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//REGDIMM, set bit 15 = 1, offset 0xFC,
	addis   0,0,0xFC00
	or	0,6,0

//do configuration read to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 15 at offset 0xFC
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFF7F    //clear bit 15, default DIMM mode off
	andi.	8,8,0xFFFF	
	or	8,9,8
	
//load DRAM port code from address 0xFE000348, DCCR B
        addis   10,0,0xFE00          // high short PCI addr of port DCCR B
        ori     10,10,0x0348        // low  short PCI addr of port DCCR B

        addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)

//DCCR B, REGMODE, bit 2, 0 = Flow_through
//                        1 = registered DIMM mode (REGDIMM on)

        andi.   11,11,0x0004        // mask DCCR B, REGMODE, bit2
	cmpwi   cr2,11,0x0004        // Do we have REGMODE=1?
        bne     cr2,RegDimmEndALL     // No, flow_through mode, REGMODE=0	
	
				      // REGMODE=1, DIMM mode on
    	oris	8,8,0x0080          // set bit 15 at offset 0xFC
	
RegDimmEndALL:
//do configuration write to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


//###################################################################
// setup enable bank0, all other banks will be disabled, clear PGMAX
//###################################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//set bit 0 = 1, offset 0xA0,
	addis   0,0,0xA000
	or	0,6,0

//do configuration read to offset A0h;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
        addis   8,0,0x0000     // clear 8
	oris	8,8,0x0100	// Enable Bank1 Bit 0 = 1
	
//do configuration write to offset A0h;
        eieio
	stw	0,0(4)
	eieio	
	stw	8,0(5)
	eieio
//#####################################################
// setup ECC on demand
//#####################################################
//	b       ECC
ecc_is_enabled:

//#####################################################
// setup SDRAM MEMORY MEMGO
//#####################################################
//preset pci slot 0 for mpc107 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

// MEMGO, set bit 19 = 1, offset 0xF0,
	addis   0,0,0xF000
	or	0,6,0

//do configuration read to offset F0h;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 19 =1 at offset 0xF0
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFFFF
	andi.	8,8,0xF7FF
	or	8,9,8 
	
	ori	8,8,0x0800    // MEMGO=1

//do configuration write to offset F0h;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)       // Go...
	eieio	

//#####################################################
// Now we have to wait >=100uS 
//#####################################################
	addis	6,0,0x0000
	addis	8,0,0x0000
	ori	8,8,0xFFFF

loopwait2:
	cmp	0,0,6,8
        bc-     12,2,loopend5	//beq

	addi	6,6,0x0001
        b	loopwait2 

loopend5:

        b	memory_runs


        
//######################################################
// Code for ECC
//######################################################

//######################################################
// According to NDA Version X.0 bits shown below must
// be set to provide inline-ECC mode. These bits are
// located at MCCR 1..4 (offset 0xF0..FC).
//                     ECC  Reg-mode MCCR
// RAM_TYPE          =  0    0        1
// EDO               =  0    0        2 (no FP/EDO-DRAM)
// PCKEN             =  0    0        1
// INLINE_WR_EN      =  1    0        2 !
// INLINE_RD_EN      =  1    0        2 !
// INLINE_ECC_OR_PAR =  0    0        2
// BUF_TYPE_0        =  1    0        4 !
// BUF_TYPE_1        =  0    1        4 !
// RMW_PAR           =  1    0        2 !
// ECC_EN            =  0    0        2 
// MEM_PERR_EN       =  1    0        - 
// MB_ECC_ERR__EN    =  0    0        - 
//
// - RDLAT timing parameter must be set to value 6
//   for inline-ECC at 83/99MHz.
// - Code lines below modify bits marked by an '!' as
//   shown above. All other bits required to run S-DRAM
//   must be initialised by calling 'init_sdram_bank0'.
// - All other bits will not be changed.
// - ECC must be called just before memgo bit is set.
// - Only valid for FASTBUS=1 and REGMODE=1.
//
//######################################################
ECC:
//preset config. addr/data addresses
	addis	4,0,0xFEC0
	ori	4,4,0x0000
	addis	5,0,0xFEE0
	ori	5,5,0x0000
	
//######################################################
// setup RDLAT=5-6,Data latency from read
// Programmed plus 1 clk for registered buffers
// Programmed plus 1 clk for DIMM mode
// Programmed plus 1 clk for ECC mode
// Only valid if being in fastmode and registered buffers
//  and therefore only at 83/99MHz.
// tCAC=30ns, 30ns*83MHz=2.49 ->3; (+1+1+1) = 6
// tCAC=30ns, 30ns*99MHz=2.97 ->3; (+1+1+1) = 6
//######################################################
//Check for FAST- and SLOWBUS	
//load DRAM port DCCR B code from address 0xFE000348
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr