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MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

// REFREC, set bits 27..24 = 0110b = 6, offset 0xF8,
	addis   0,0,0xF800
	or	0,6,0

//do configuration read to offset F8h;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bits 27..24 at offset 0xF8
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFFFF
	andi.	8,8,0xFFF0	//clear bits 27..24
	or	8,9,8
	
	
	
//load DRAM port code from address 0xFE000348
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)

// FASTBUS, bit 3, 0 = SLOW_BUSFREQ (mask 0x30)
//                 1 = FAST_BUSFREQ (mask 0xC0)
// 66MHz = 0x30; DRAM port values for SLOW_BUSFREQ bus clock
// 83MHz = 0x20  (mask = 0x30)
// 99MHz = 0x10
// res.  = 0x00
// 66MHz = 0xC0; DRAM port values for FAST_BUSFREQ bus clock
// 83MHz = 0x80  (mask = 0xC0)
// 99MHz = 0x40
// res.  = 0x00
        andi.   11,11,0x0008        // mask FASTBUS bit3
        
        cmpwi   cr2,11,0x0008        // Do we have FASTBUS=1?
        beq     cr2,Refrec99FAST      // Yes, FASTBUS=1 branch to FAST_BUSFREQ
        
        
        
//SLOW_BUSFREQ   
    
Refrec99SLOW:
				      // No, FASTBUS=0=SLOW_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x0030        // mask bits SLOW_BUSFREQ

				      // Check for MHz...
        cmpwi   cr2,11,0x0030        // Do we have 66MHz?
        beq     cr2,Refrec66SLOW      // Yes, jmp if we have 66MHz 
         
        cmpwi   cr2,11,0x0020        // Do we have 83MHz?
        beq     cr2,Refrec83SLOW      // Yes, jmp if we have 83MHz
        
				      // Must be 99MHz...
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 27..24 at offset 0xF8
	ori	8,8,0x0009          //REFREC = 9; 99MHz
	b       RefrecEndALL

Refrec83SLOW:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 27..24 at offset 0xF8
	ori	8,8,0x0008          //REFREC = 8; 83MHz
	b       RefrecEndALL
	
Refrec66SLOW:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 27..24 at offset 0xF8
	ori	8,8,0x0006          //REFREC = 6; 66MHz
	b       RefrecEndALL



//FAST_BUSFREQ   
    
Refrec99FAST:
				      // No, FASTBUS=1=FAST_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x00C0        // mask bits FAST_BUSFREQ

				      // Check for MHz...
        cmpwi   cr2,11,0x00C0        // Do we have 66MHz?
        beq     cr2,Refrec66FAST      // Yes, jmp if we have 66MHz 
         
        cmpwi   cr2,11,0x0080        // Do we have 83MHz?
        beq     cr2,Refrec83FAST      // Yes, jmp if we have 83MHz
        
				      // Must be 99MHz...
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 27..24 at offset 0xF8
	ori	8,8,0x0009          //REFREC = 9; 99MHz
	b       RefrecEndALL

Refrec83FAST:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 27..24 at offset 0xF8
	ori	8,8,0x0008          //REFREC = 8; 83MHz
	b       RefrecEndALL
	
Refrec66FAST:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 27..24 at offset 0xF8
	ori	8,8,0x0006          //REFREC = 6; 66MHz



	
RefrecEndALL:
//do configuration write to offset F8h;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


//#############################################################
// setup RDLAT=2-3,Data latency from read
// Programmed plus 1 clk for registered buffers
// Programmed plus 1 clk for DIMM mode
// tCAC=30ns, 30ns*66MHz=1.98 ->2; (+1 for Registered +1 for DIMM)
// tCAC=30ns, 30ns*83MHz=2.49 ->3; (+1 for Registered +1 for DIMM)
// tCAC=30ns, 30ns*99MHz=2.97 ->3; (+1 for Registered +1 for DIMM)
//#############################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

// RDLAT, set bits 23..20 = 0011b = 2+1+X, offset 0xF8,
	addis   0,0,0xF800
	or	0,6,0

//do configuration read to offset F8h;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bits 23..20 at offset 0xF8
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFFFF
	andi.	8,8,0x0FFF	// clear bits 23..20
	or	8,9,8
	
	
//Check for FAST- and SLOWBUS	
//load DRAM port code from address 0xFE000348
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)

        
// FASTBUS, bit 3, 0 = SLOW_BUSFREQ (mask 0x30)
//                 1 = FAST_BUSFREQ (mask 0xC0)
// 66MHz = 0x30; DRAM port values for SLOW_BUSFREQ bus clock
// 83MHz = 0x20  (mask = 0x30)
// 99MHz = 0x10
// res.  = 0x00
// 66MHz = 0xC0; DRAM port values for FAST_BUSFREQ bus clock
// 83MHz = 0x80  (mask = 0xC0)
// 99MHz = 0x40
// res.  = 0x00
        andi.   11,11,0x0008        // mask FASTBUS bit3
	cmpwi   cr2,11,0x0008        // Do we have FASTBUS=1?
        beq     cr2,rdlat66FAST       // Yes, FASTBUS=1 branch to FAST_BUSFREQ        
        
        

//SLOW_BUSFREQ

rdlat66SLOW:                          
				      // here we have upper and/or
				      // lower module without DIMM mode

				      // No, FASTBUS=0=SLOW_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x0030        // mask bits SLOW_BUSFREQ
				      // Check for 66MHz
        cmpwi   cr2,11,0x0030        // Do we have 66MHz?    
        bne     cr2,rdlat8399SLOW     // No, jmp if we have 83/99MHz
        
        
        
    //Check for registered or flow_thru mode
    //load DRAM port code from address 0xFE000348
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          
        lbz     11,0(10)            
        eieio                                 
        andi.   11,11,0x0004        // mask DCCR B, REGMODE, bit2
        cmpwi   cr2,11,0x0004        // Do we have REGMODE=1?
        beq     cr2,REGMODE66_REG_SLOW // Yes, REGMODE=1 branch to REGMODE66_REG_SLOW       

    // 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
    // RDLAT = 2+1; 66MHz, flow-thru
	ori	8,8,0x3000          //RDLAT = 2+1+0 = 3; 66MHz
	b       rdlatEndALL

REGMODE66_REG_SLOW:        

    // 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
    // RDLAT = 2+1+1; 66MHz, registered
	ori	8,8,0x4000          //RDLAT = 2+1+1 = 4; 66MHz
	b       rdlatEndALL
	
	
	
	
rdlat8399SLOW:

    //Check for registered or flow_thru mode
    //load DRAM port code from address 0xFE000348
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          
        lbz     11,0(10)            
        eieio                                 
        andi.   11,11,0x0004        // mask REGMODE bit2
        cmpwi   cr2,11,0x0004        // Do we have REGMODE=1?
        beq     cr2,REGMODE8399_REG_SLOW // Yes, REGMODE=1 branch to REGMODE8399_REG_SLOW        

    // 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
    // RDLAT = 3+1; 83/99MHz, flow_thru
	ori	8,8,0x4000          //RDLAT = 3+1+0 = 4; 83/99MHz
	b       rdlatEndALL

REGMODE8399_REG_SLOW:        

    // 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
    // RDLAT = 3+1+1; 83/99MHz, registered
	ori	8,8,0x5000          //RDLAT = 3+1+1 = 5; 83/99MHz
	b       rdlatEndALL
	


	

//FAST_BUSFREQ

rdlat66FAST:                          
				      // here we have -NO-upper and/or
				      // lower module with DIMM mode

				      // No, FASTBUS=1=FAST_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x00C0        // mask bits FAST_BUSFREQ

				      // Check for 66MHz
	cmpwi   cr2,11,0x00C0        // Do we have 66MHz?
        bne     cr2,rdlat8399FAST     // No, jmp if we have 83/99MHz


    //Check for registered or flow_thru mode
    //load DRAM port code from address 0xFE000348
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          
        lbz     11,0(10)            
        eieio                                 
        andi.   11,11,0x0004        // mask REGMODE bit2
        cmpwi   cr2,11,0x0004        // Do we have REGMODE=1?
        beq     cr2,REGMODE66_REG_FAST // Yes, REGMODE=1 branch to REGMODE66_REG_FAST        

    // 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
    // RDLAT = 3+1; 66MHz, flow_thru
	ori	8,8,0x4000          //RDLAT = 3+1+0 = 4; 66MHz
	b       rdlatEndALL

REGMODE66_REG_FAST:        

    // 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
    // RDLAT = 3+1+1; 66MHz, registered
	ori	8,8,0x5000          //RDLAT = 3+1+1 = 5; 66MHz
	b       rdlatEndALL



rdlat8399FAST:

    //Check for registered or flow_thru mode
    //load DRAM port code from address 0xFE000348
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          
        lbz     11,0(10)            
        eieio                                 
        andi.   11,11,0x0004        // mask REGMODE bit2
        cmpwi   cr2,11,0x0004        // Do we have REGMODE=1?
        beq     cr2,REGMODE8399_REG_FAST // Yes, REGMODE=1 branch to REGMODE8399_REG_FAST     

    // 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
    // RDLAT = 3+1; 83/99MHz, flow_thru
	ori	8,8,0x4000          //RDLAT = 3+1+0 = 4; 83/99MHz
	b       rdlatEndALL

REGMODE8399_REG_FAST:        

    // 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
    // RDLAT = 3+1+1; 83/99MHz, registered
	ori	8,8,0x5000          //RDLAT = 3+1+1 = 5; 83/99MHz
	b       rdlatEndALL


	
	
rdlatEndALL:
//do configuration write to offset F8h;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


////########################################################
// setup PRETOACT=2-3, Precharge to activate interval
// tRP=30ns, 30ns*66MHz=1.98 ->2
// tRP=30ns, 30ns*83MHz=2.49 ->3
// tRP=30ns, 30ns*99MHz=2.97 ->3
//#########################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//PRETOACT, set bits 31..28, offset 0xFC,
	addis   0,0,0xFC00
	or	0,6,0

//do configuration read to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bits 31..28 at offset 0xFC
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFFFF
	andi.	8,8,0xFF0F	// clear bits 31..28
	or	8,9,8
	
//load DRAM port code from address 0xFE000348
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)

// FASTBUS, bit 3, 0 = SLOW_BUSFREQ (mask 0x30)
//                 1 = FAST_BUSFREQ (mask 0xC0)
// 66MHz = 0x30; DRAM port values for SLOW_BUSFREQ bus clock
// 83MHz = 0x20  (mask = 0x30)
// 99MHz = 0x10
// res.  = 0x00
// 66MHz = 0xC0; DRAM port values for FAST_BUSFREQ bus clock
// 83MHz = 0x80  (mask = 0xC0)
// 99MHz = 0x40
// res.  = 0x00
        andi.   11,11,0x0008        // mask FASTBUS bit3
        
        cmpwi   cr2,11,0x0008        // Do we have FASTBUS=1?
        beq     cr2,Pretoact66FAST    // Yes, FASTBUS=1 branch to FAST_BUSFREQ    



// SLOW_BUSFREQ

Pretoact66SLOW:
				      // No, FASTBUS=0=SLOW_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x0030        // mask bits SLOW_BUSFREQ

				      // Check for 66MHz
        cmpwi   cr2,11,0x0030        // Do we have 66MHz?
        bne     cr2,Pretoact8399SLOW  // No, jmp if we have 83/99MHz

// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// PRETOACT = 2; 66MHz
	ori	8,8,0x0020          // PRETOACT = 2; 66MHz
	b       PretoactEndALL

Pretoact8399SLOW:
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// PRETOACT = 3; 83/99MHz
	ori	8,8,0x0030          // PRETOACT = 3; 83/99MHz
	b       PretoactEndALL
	

	
//FAST_BUSFREQU	
	
Pretoact66FAST:
	
				      // No, FASTBUS=1=FAST_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x00C0        // mask bits FAST_BUSFREQ

				      // Check for 66MHz
        cmpwi   cr2,11,0x00C0        // Do we have 66MHz?
        bne     cr2,Pretoact8399FAST  // No, jmp if we have 83/99MHz

// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// PRETOACT = 2; 66MHz
	ori	8,8,0x0020          // PRETOACT = 2; 66MHz
	b       PretoactEndALL

Pretoact8399FAST:
// 8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
// PRETOACT = 3; 83/99MHz
	ori	8,8,0x0030          // PRETOACT = 3; 83/99MHz
	
	
	
PretoactEndALL:
//do configuration write to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio

//#########################################################
// setup ACTOPRE=4-6, Activate to precharge interval
// tRAS(min)=60ns, 60ns*66MHz=3.96 ->4
// tRAS(min)=60ns, 60ns*83MHz=4.98 ->5
// tRAS(min)=60ns, 60ns*99MHz=5.94 ->6
//#########################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//ACTTOPRE, set bits 27..24, offset 0xFC,