start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	
	
	
//load DCCR A code from address 0xFE000308, mask 0x0F onboard memory
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0308        // low  short PCI addr of port

        addis   11,0,0x0000          // clear 11, (11)=0x00000000
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)
        
// 0001b =  64MB, 0x03FFFFFF, SDRAM
// 0010b = 128MB, 0x07FFFFFF, SDRAM
// 0011b = 256MB, 0x0FFFFFFF, SDRAM
        andi.   11,11,0x000F        // mask onboard memory bits	
	
SDRAM256_END:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
        cmpwi   cr2,11,0x0003        // Do we have 256MB?
        bne+    cr2,SDRAM128_END      // No, check do we have 128MHz?

        oris	8,8,0xFF00          // Yes, 256MB...
	lis	15, 0x1000		/* Memory Size accumulator = 256 MB */
        b       Sel_size_end

SDRAM128_END:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
        cmpwi   cr2,11,0x0002        // Do we have 128MB?
        bne+    cr2,SDRAM64_END       // No, check do we have 64MB?

        oris	8,8,0x7F00          // Yes, 128MB...
	lis	15, 0x0800		/* Memory size accumulator = 128 MB */
        b       Sel_size_end

SDRAM64_END:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
	oris	8,8,0x3F00          // Must be 64MB..already default
	lis	15, 0x0400		/* Memory size accumulator = 64 MB */

Sel_size_end:	

//do configuration write to offset 90h,
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

// mem_end_ext03, offset 98, 7..0  = 00XXYYZZ, 0 =0x98XX0080;
	addis   0,0,0x9800
	or	0,6,0

//do configuration read to offset 98h, little endian!!!
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
//clear bits 1..0, bank 0 end at 64MB or 128MB or 256MB onboard memory
	or	9,8,8	// move (8)->(9)
	andis.	9,9,0xFCFF    // (9) = 0xAB'CD0000
	andi.	8,8,0xFFFF    // (8) = 0x0000EFGH
	or	8,9,8        // (8) = 0xAB'CDEFGH


//do configuration write to offset 98h,
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio



//##################################################################################
// setup row address bit count for bank 0, onboard SDRAM
//  64MB: 00b  64MBit, 4 banks, 12x 9x4
// 128MB: 00b 128MBit, 4 banks, 12x10x4
// 256MB: 10b 256MBit, 4 banks, 13x10x4
//##################################################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

// rowcnt 00b, offset 0xF0,  1..0  = W2XXYYZZ, 0 =0xF0XX0080;
	addis   0,0,0xF000
	or	0,6,0

//do configuration read to offset F0h to preserve bits 31..2,
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
//clear bits 1..0 to 00b, for a  64MBit 4 internal banks, 12x 9x4, SDRAM
//clear bits 1..0 to 00b, for a 128MBit 4 internal banks, 12x10x4, SDRAM
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFCFF    // (9) = 0xAB'CD0000
	andi.	8,8,0xFFFF    // (8) = 0x0000EFGH
	or	8,9,8        // (8) = 0xAB'CDEFGH
                                // (8) = 0x0B'CD0000
                                
                                // now default for 64/128MB set
                                
//load DCCR A code from address 0xFE000308, mask 0x0F onboard memory
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0308        // low  short PCI addr of port

        addis   11,0,0x0000          // clear 11, (11)=0x00000000
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)
        
// 0001b =  64MB, 0x03FFFFFF, SDRAM
// 0010b = 128MB, 0x07FFFFFF, SDRAM
// 0011b = 256MB, 0x0FFFFFFF, SDRAM
        andi.   11,11,0x000F        // mask onboard memory bits	
	
SDRAM256_ROW:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//set bits 1..0 to 10b, for a  256MBit 4 internal banks, 13x10x4, SDRAM
        cmpwi   cr2,11,0x0003        // Do we have 256MB?
        bne+    cr2,Sel_row_end       // No, check do we have 128MHz?

        oris	8,8,0x0200          // Yes, 256MBit 4 internal banks, 13x10x4              
Sel_row_end:

//do configuration write to offset F0h, little endian!!!
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


//#####################################################
// setup refresh interval timing REFINT for SDRAM
// 15.2uS for 66MHz Bus Clock, 4096 cycles/64ms, 1000=0x0384
// 14.5uS for 83MHz Bus Clock, 1200=0x04B0
// 15.0uS for 99MHz Bus Clock, 1500=0x05DC
// 256MBit S-DRAM only:
// 7.6uS for 66MHz Bus Clock, 8192 cycles/64ms, 500=0x01F4
// 7.2uS for 83MHz Bus Clock, 8192 cycles/64ms, 600=0x0258
// 7.6uS for 99MHz Bus Clock, 8192 cycles/64ms, 750=0x02ee
//
// For making software more easy it is assumed, that
// at 99MHz 256MByte lower S-DRAM und 512MByte upper
// S-DRAM Modules are mounted. No differentiation done!
//#####################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//REFINT, offset 0xF4, 15..2 = 03E8YYZZ refresh
	addis   0,0,0xF400
	or	0,6,0

//do configuration read to offset F4h to preserve bits 31..16,1..0, little endian!!!
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//->refresh every 1000 clocks at 66MHz = ~13.6uS
//->refresh every 1200 clocks at 83MHz = ~14.5uS
//->refresh every 1500 clocks at 99MHz = ~15.0uS
//at 256MBit:
//->refresh every 500 clocks at 66MHz = ~7.6uS
//->refresh every 600 clocks at 83MHz = ~7.2uS
//->refresh every 750 clocks at 99MHz = ~7.6uS
//
//clear bit 15..2
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0x0300
	andi.	8,8,0xFFFF
	or	8,9,8



//load DRAM port code from address 0xFE000348, mask 0xC0/0x30 for speed
// and FASTBUS bit3 for selector of mask SLOW_BUSFREQ (mask 0x30) or 
// FAST_BUSFREQ (mask 0xC0)
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)

// FASTBUS, bit 3, 0 = SLOW_BUSFREQ (mask 0x30)
//                 1 = FAST_BUSFREQ (mask 0xC0)
// 66MHz = 0x30; DRAM port values for SLOW_BUSFREQ bus clock
// 83MHz = 0x20  (mask = 0x30)
// 99MHz = 0x10
// res.  = 0x00
// 66MHz = 0xC0; DRAM port values for FAST_BUSFREQ bus clock
// 83MHz = 0x80  (mask = 0xC0)
// 99MHz = 0x40
// res.  = 0x00
        andi.   11,11,0x0008        // mask FASTBUS bit3
        
        cmpwi   cr2,11,0x0008        // Do we have FASTBUS=1?
        beq     cr2,Refresh99FAST     // Yes, FASTBUS=1 branch to FAST_BUSFREQ


// SLOW_BUSFREQ
				      // No, FASTBUS=0=SLOW_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x0030        // mask bits SLOW_BUSFREQ
        
Refresh99SLOW:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bit 15..2 and set 0x5DC, shifted 2times left equals 0x1770
        cmpwi   cr2,11,0x0010        // Do we have 99MHz?
        bne     cr2,Refresh83SLOW     // No, check do we have 83MHz?

        oris	8,8,0xB80B          // Yes, 99MHz...7.6uS..easy fix!
        b       refresh_end_all

Refresh83SLOW:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bit 15..2 and set 0x4B0, shifted 2times left equals 0x12C0
        cmpwi   cr2,11,0x0020        // Do we have 83MHz?
        bne     cr2,Refresh66SLOW     // No, check do we have 66MHz?

        oris	8,8,0xC012          // Yes, 83MHz...
        b       refresh_end_all

Refresh66SLOW:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bit 15..2 and set 0x384, shifted 2times left equals 0x0E10
//default timing for 66MHz!
	oris	8,8,0x100E          // Yes, 66MHz
	b       refresh_end_all    




//FAST_BUSFREQ

Refresh99FAST:
				      // No, FASTBUS=1=FAST_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x00C0        // mask bits FAST_BUSFREQ
        
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bit 15..2 and set 0x5DC, shifted 2times left equals 0x1770
        cmpwi   cr2,11,0x0040        // Do we have 99MHz?
        bne     cr2,Refresh83FAST     // No, check do we have 83MHz?

        oris	8,8,0xB80B          // Yes, 99MHz...7.6uS..easy fix!
        b       refresh_end_all

Refresh83FAST:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bit 15..2 and set 0x4B0, shifted 2times left equals 0x12C0
        cmpwi   cr2,11,0x0080        // Do we have 83MHz?
        bne     cr2,Refresh66FAST     // No, check do we have 66MHz?

        oris	8,8,0xC012          // Yes, 83MHz...
        b       refresh_end_all

Refresh66FAST:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bit 15..2 and set 0x384, shifted 2times left equals 0x0E10
//default timing for 66MHz!
	oris	8,8,0x100E          // Yes, 66MHz




refresh_end_all:
//do configuration write to offset F4h, little endian value!!!
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio



//##################################################################
//-----------------------------66MHz--------------------------------
// setup SDMODE SDRAM mode register
// SDRAM: 4Banks, 64/128/256MBit, /CAS latency 2, burst length 4, 
//        sequencial, 4096 refresh/64ms   
// Setup:(op-code   : 00000b)  ; always all zero at MPC107
//        CAS lat.  :   010b   ; 2
//        wraptype  :     0b   ; sequencial for PowerPC
//        wraplength:   010b   ; 4
//        ------------------------
//        ->        (bit14)-010.0010-(bit8)
//        -> xxxx.xxxx.xxxx.xxxx.x010.0010.xxxx.xxxxb (= *(0xFC) )
//        -> 0xXXXX22XX ;big endian calculation
//        -> 0xXX22XXXX ;little endian value t. b. written
//        -> 0x00220000 ;value to be "ORed"
//
//-----------------------------83/99MHz-----------------------------
// SDRAM: 4Banks, 64/128/256MBit, /CAS latency 3, burst length 4, 
//        sequencial, 4096 refresh/64ms   
// Setup:(op-code   : 00000b)  ; always all zero at MPC107
//        CAS lat.  :   011b   ; 3
//        wraptype  :     0b   ; sequencial for PowerPC
//        wraplength:   010b   ; 4
//        ------------------------
//        ->        (bit14)-011.0010-(bit8)
//        -> xxxx.xxxx.xxxx.xxxx.x011.0010.xxxx.xxxxb (= *(0xFC) )
//        -> 0xXXXX32XX ;big endian calculation
//        -> 0xXX32XXXX ;little endian value t. b. written
//        -> 0x00320000 ;value to be "ORed"
//------------------------------------------------------------------
//   debug:  0x08320000
// 100MHz SDRAM is used (M5M4V64S30ATP-10, KM48S8030BT-G/FL)
// (modify here for other sizes/speeds)
//##################################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//SDMODE, value=010.0.010 binary , offset 0xFC
	addis   0,0,0xFC00
	or	0,6,0

//do configuration read to offset FCh to preserve bits 31..15,7..0 little endian!!!
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bits 14..8, SDMODE= all to 0
	or	9,8,8	 //move (8)->(9)
	andis.	9,9,0xFF80
	andi.	8,8,0xFFFF    
	or	8,9,8


//load DRAM port code from address 0xFE000348,
        addis   10,0,0xFE00          // high short PCI addr of port
        ori     10,10,0x0348        // low  short PCI addr of port

        addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value
        eieio                         // for 604(e)


// FASTBUS, bit 3, 0 = SLOW_BUSFREQ (mask 0x30)
//                 1 = FAST_BUSFREQ (mask 0xC0)
// 66MHz = 0x30; DRAM port values for SLOW_BUSFREQ bus clock
// 83MHz = 0x20  (mask = 0x30)
// 99MHz = 0x10
// res.  = 0x00
// 66MHz = 0xC0; DRAM port values for FAST_BUSFREQ bus clock
// 83MHz = 0x80  (mask = 0xC0)
// 99MHz = 0x40
// res.  = 0x00
        andi.   11,11,0x0008        // mask FASTBUS bit3
        
        cmpwi   cr2,11,0x0008        // Do we have FASTBUS=1?
        beq     cr2,SDmode66FAST      // Yes, FASTBUS=1 branch to FAST_BUSFREQ



// SLOW_BUSFREQ
				      // No, FASTBUS=0=SLOW_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x0030        // mask bits SLOW_BUSFREQ

				      // Check for 66MHz
        cmpwi   cr2,11,0x0030        // Do we have 66MHz?
        bne     cr2,SDmode8399SLOW    // No, jmp if we have 83/99MHz

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//or value 0x00220000 to contents of 8
//bits 14..8 = SDMODE
	oris	8,8,0x0022          //Yes, 66MHz
	b       SDmodeEndAll

SDmode8399SLOW:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//or value 0x00320000 to contents of 8
//bits 14..8 = SDMODE
	oris	8,8,0x0032          // 83/99MHz
	b       SDmodeEndAll  
	
	    
	    
	      
// FAST_BUSFREQ

SDmode66FAST:
				      // No, FASTBUS=1=FAST_BUSFREQ
	addis   11,0,0x0000          // clear 11, (11)=0
        lbz     11,0(10)            // load DRAM port value again
        eieio                         // for 604(e)
        andi.   11,11,0x00C0        // mask bits FAST_BUSFREQ

				      // Check for 66MHz
        cmpwi   cr2,11,0x00C0        // Do we have 66MHz?
        bne     cr2,SDmode8399FAST    // No, jmp if we have 83/99MHz

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//or value 0x00220000 to contents of 8
//bits 14..8 = SDMODE
	oris	8,8,0x0022          //Yes, 66MHz
	b       SDmodeEndAll

SDmode8399FAST:
//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//or value 0x00320000 to contents of 8
//bits 14..8 = SDMODE
	oris	8,8,0x0032          // 83/99MHz



SDmodeEndAll:
//do configuration write to offset FCh, little endian value!!!
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


//#########################################################
// Now the timing relevant parameters are set. These
// parameters will define SDRAM access speed.
// An 2-1-1-1 burst access is planned for a 66MHz bus.
// An 3-1-1-1 burst access is planned for a 83/99MHz bus.
// Dreaming that HW testing will define the settings finaly!
// 66MHz, 83MHz, 99MHz bus clock are pre-calculated, set
// now dynamically depending on the bus frequency.
// 100MHz SDRAM is assembled (M5M4V64S30ATP-10) and
// data sheet is used for calculation.
//#########################################################
//#########################################################
// setup REFREC=6-9,refresh recovery interval
// tRC=90ns, 90ns*66MHz=5.94 ->6
// tRC=90ns, 90ns*83MHz=7.47 ->8
// tRC=90ns, 90ns*99MHz=8.91 ->9
//#########################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080